KMAC/UNMASKED Simulation Results

Sunday May 25 2025 00:06:37 UTC

GitHub Revision: `2a67071`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.027m	10.520ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.590s	56.953us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.590s	135.483us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	15.880s	2.726ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.700s	139.013us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.760s	1.203ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.590s	135.483us	20	20	100.00
		kmac_csr_aliasing	6.700s	139.013us	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.180s	37.671us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.800s	26.621us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	48.966m	164.264ms	50	50	100.00
V2	burst_write	kmac_burst_write	16.113m	196.773ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	29.320m	92.437ms	5	5	100.00
		kmac_test_vectors_sha3_256	26.820m	116.528ms	5	5	100.00
		kmac_test_vectors_sha3_384	20.861m	77.607ms	5	5	100.00
		kmac_test_vectors_sha3_512	17.876m	96.834ms	5	5	100.00
		kmac_test_vectors_shake_128	2.697m	91.319ms	5	5	100.00
		kmac_test_vectors_shake_256	30.151m	346.868ms	5	5	100.00
		kmac_test_vectors_kmac	4.310s	449.359us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.050s	344.300us	5	5	100.00
V2	sideload	kmac_sideload	5.896m	23.267ms	50	50	100.00
V2	app	kmac_app	5.456m	26.804ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.021m	27.117ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	4.870m	57.492ms	50	50	100.00
V2	error	kmac_error	6.531m	159.086ms	49	50	98.00
V2	key_error	kmac_key_error	15.240s	10.224ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.276m	10.104ms	31	50	62.00
V2	edn_timeout_error	kmac_edn_timeout_error	39.920s	4.293ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	37.260s	5.180ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	42.640s	24.595ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	59.060s	3.881ms	50	50	100.00
V2	stress_all	kmac_stress_all	35.779m	226.464ms	50	50	100.00
V2	intr_test	kmac_intr_test	2.450s	32.312us	50	50	100.00
V2	alert_test	kmac_alert_test	2.380s	445.083us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.900s	507.452us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.900s	507.452us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.590s	56.953us	5	5	100.00
		kmac_csr_rw	2.590s	135.483us	20	20	100.00
		kmac_csr_aliasing	6.700s	139.013us	5	5	100.00
		kmac_same_csr_outstanding	4.140s	119.215us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.590s	56.953us	5	5	100.00
		kmac_csr_rw	2.590s	135.483us	20	20	100.00
		kmac_csr_aliasing	6.700s	139.013us	5	5	100.00
		kmac_same_csr_outstanding	4.140s	119.215us	20	20	100.00
V2		TOTAL			720	740	97.30
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.360s	813.847us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.360s	813.847us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.360s	813.847us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.360s	813.847us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.430s	180.448us	13	20	65.00
V2S	tl_intg_err	kmac_sec_cm	1.029m	18.748ms	5	5	100.00
		kmac_tl_intg_err	5.790s	363.070us	15	20	75.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.790s	363.070us	15	20	75.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	59.060s	3.881ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.027m	10.520ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	5.896m	23.267ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.360s	813.847us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.029m	18.748ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.029m	18.748ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.029m	18.748ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.027m	10.520ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	59.060s	3.881ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.029m	18.748ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.993m	31.094ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.027m	10.520ms	50	50	100.00
V2S		TOTAL			63	75	84.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.101m	2.098ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			902	940	95.96

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.78	97.08	94.46	100.00	73.55	95.90	99.35	96.13

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 11 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 6 failures.

1.kmac_shadow_reg_errors_with_csr_rw.91481437586714695980136718841805704074734213312360062724900185927543049646245
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[45] & 'hffffffff)))'
  UVM_ERROR @  92315714 ps: (kmac_csr_assert_fpv.sv:525) [ASSERT FAILED] prefix_6_rd_A
  UVM_INFO @  92315714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.kmac_shadow_reg_errors_with_csr_rw.28144561589469352723481859036254704824059319358459047188860346462112169910794
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[49] & 'hffffffff)))'
  UVM_ERROR @  14810681 ps: (kmac_csr_assert_fpv.sv:545) [ASSERT FAILED] prefix_10_rd_A
  UVM_INFO @  14810681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test kmac_tl_intg_err has 5 failures.

1.kmac_tl_intg_err.50613393346483828396044272591227367865743795183307789701952325465550762909515
Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/1.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[47] & 'hffffffff)))'
  UVM_ERROR @  10360564 ps: (kmac_csr_assert_fpv.sv:535) [ASSERT FAILED] prefix_8_rd_A
  UVM_INFO @  10360564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.kmac_tl_intg_err.97295489611524239523158417118328201442504572360614934956044437238239482952808
Line 75, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/3.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[44] & 'hffffffff)))'
  UVM_ERROR @ 135622624 ps: (kmac_csr_assert_fpv.sv:520) [ASSERT FAILED] prefix_5_rd_A
  UVM_INFO @ 135622624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 6 failures:
- Test kmac_stress_all_with_rand_reset has 6 failures.
  - 0.kmac_stress_all_with_rand_reset.11699358217349782898888419513532149812365841680596247593281846477419077443880
    Line 80, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  40134622 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
  UVM_INFO @  40134622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.kmac_stress_all_with_rand_reset.11785617644703338339894565515770984586787534189005062480775633674974983873423
    Line 121, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2255753283 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 2255753283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 4 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 4 failures:
- Test kmac_sideload_invalid has 4 failures.
  - 0.kmac_sideload_invalid.8362359139754406699194565983592835182107456527594579422145133242530736236562
    Line 77, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10061582460 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x1bbbb000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
  UVM_INFO @ 10061582460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 31.kmac_sideload_invalid.29681054185521807149483971718126780768058719482181114824164922011005739652175
    Line 76, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/31.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10113684361 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x30076000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
  UVM_INFO @ 10113684361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 4 failures:
- Test kmac_sideload_invalid has 4 failures.
  - 6.kmac_sideload_invalid.2535259358188897765553963858114162373876824499185757943411834301235735678749
    Line 73, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/6.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10013649264 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xedbb000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
  UVM_INFO @ 10013649264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 22.kmac_sideload_invalid.37456399664676955234594963292105063413264364171885510618543791046396306198543
    Line 73, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/22.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10008025391 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x5aab7000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
  UVM_INFO @ 10008025391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 0.kmac_shadow_reg_errors_with_csr_rw.50790289556890570229394794950705996309775624146016144969363456471985700402702
    Line 85, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @   8078210 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (4210089018 [0xfaf0dc3a] vs 0 [0x0]) Regname: kmac_reg_block.prefix_6 reset value: 0x0
  UVM_INFO @   8078210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 4.kmac_sideload_invalid.50013534360716489560189503942424027597018059973343192009291861072282789435322
    Line 94, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/4.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10231814164 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb58fc000, Comparison=CompareOpEq, exp_data=0x1, call_count=21)
  UVM_INFO @ 10231814164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 11.kmac_sideload_invalid.61395733196868949768480505729285016593752146072985917293341974842939427378340
    Line 87, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/11.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10923148862 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x8a8d8000, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
  UVM_INFO @ 10923148862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 12.kmac_sideload_invalid.36279451817684490664987489614677233215904540864105481778495661913396087025930
    Line 76, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/12.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10217486406 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xfc676000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
  UVM_INFO @ 10217486406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 18.kmac_sideload_invalid.103156610375223645659312068912991875466386098145146970900647121613044988383738
    Line 82, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/18.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10307820595 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xffada000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
  UVM_INFO @ 10307820595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 20.kmac_sideload_invalid.69934250808044348996155184480652863587490552108332312252616265881782736192806
    Line 89, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/20.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10104470547 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x543a4000, Comparison=CompareOpEq, exp_data=0x1, call_count=17)
  UVM_INFO @ 10104470547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_error has 1 failures.
  - 21.kmac_error.34893384650299427261836946495447641079458258877969366278880418023622211142915
    Line 181, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/21.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=26) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 23.kmac_sideload_invalid.33467160369942920510541498435801977559385144118800337283482952231368978443161
    Line 101, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/23.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10914549587 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xfe7e8000, Comparison=CompareOpEq, exp_data=0x1, call_count=26)
  UVM_INFO @ 10914549587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 24.kmac_sideload_invalid.86021954152616876211796027929934824550871886491600261445214076910793354163025
    Line 77, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/24.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10058622567 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xa9c31000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
  UVM_INFO @ 10058622567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 26.kmac_sideload_invalid.44169813740776502449021756114157777713034808268659265652551052686299141926287
    Line 82, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/26.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10313160123 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xca4000, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
  UVM_INFO @ 10313160123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 32.kmac_sideload_invalid.35538763257677761193562798195433864452676724674666676108897133479224223232384
    Line 87, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/32.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10238603422 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x38033000, Comparison=CompareOpEq, exp_data=0x1, call_count=13)
  UVM_INFO @ 10238603422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 33.kmac_sideload_invalid.22420657714978039451257715163127409250580475118142666794241670714434244093761
    Line 74, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/33.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10070884674 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x2bae2000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 10070884674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=24) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 44.kmac_sideload_invalid.77663329438558475463763282436065211381498793845144167415554986053089638582131
    Line 97, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/44.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10383977295 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x25adf000, Comparison=CompareOpEq, exp_data=0x1, call_count=24)
  UVM_INFO @ 10383977295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```