2a67071| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | otbn_smoke | 13.000s | 47.654us | 1 | 1 | 100.00 |
| V1 | single_binary | otbn_single | 29.000s | 109.169us | 100 | 100 | 100.00 |
| V1 | csr_hw_reset | otbn_csr_hw_reset | 10.000s | 12.047us | 5 | 5 | 100.00 |
| V1 | csr_rw | otbn_csr_rw | 11.000s | 17.282us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otbn_csr_bit_bash | 12.000s | 35.727us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otbn_csr_aliasing | 10.000s | 16.540us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otbn_csr_mem_rw_with_rand_reset | 14.000s | 62.516us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otbn_csr_rw | 11.000s | 17.282us | 20 | 20 | 100.00 |
| otbn_csr_aliasing | 10.000s | 16.540us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otbn_mem_walk | 43.000s | 16.213ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otbn_mem_partial_access | 20.000s | 1.103ms | 5 | 5 | 100.00 |
| V1 | TOTAL | 166 | 166 | 100.00 | |||
| V2 | reset_recovery | otbn_reset | 29.000s | 106.785us | 10 | 10 | 100.00 |
| V2 | multi_error | otbn_multi_err | 27.677s | 0 | 1 | 0.00 | |
| V2 | back_to_back | otbn_multi | 1.783m | 1.358ms | 10 | 10 | 100.00 |
| V2 | stress_all | otbn_stress_all | 1.250m | 282.722us | 10 | 10 | 100.00 |
| V2 | lc_escalation | otbn_escalate | 19.000s | 97.491us | 59 | 60 | 98.33 |
| V2 | zero_state_err_urnd | otbn_zero_state_err_urnd | 11.000s | 26.720us | 5 | 5 | 100.00 |
| V2 | sw_errs_fatal_chk | otbn_sw_errs_fatal_chk | 26.000s | 72.562us | 10 | 10 | 100.00 |
| V2 | alert_test | otbn_alert_test | 9.000s | 18.966us | 50 | 50 | 100.00 |
| V2 | intr_test | otbn_intr_test | 12.000s | 20.768us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | otbn_tl_errors | 12.000s | 189.202us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otbn_tl_errors | 12.000s | 189.202us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otbn_csr_hw_reset | 10.000s | 12.047us | 5 | 5 | 100.00 |
| otbn_csr_rw | 11.000s | 17.282us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 10.000s | 16.540us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 11.000s | 19.079us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otbn_csr_hw_reset | 10.000s | 12.047us | 5 | 5 | 100.00 |
| otbn_csr_rw | 11.000s | 17.282us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 10.000s | 16.540us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 11.000s | 19.079us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 244 | 246 | 99.19 | |||
| V2S | mem_integrity | otbn_imem_err | 12.000s | 30.949us | 10 | 10 | 100.00 |
| otbn_dmem_err | 18.000s | 686.598us | 15 | 15 | 100.00 | ||
| V2S | internal_integrity | otbn_alu_bignum_mod_err | 25.000s | 392.739us | 5 | 5 | 100.00 |
| otbn_controller_ispr_rdata_err | 12.000s | 224.339us | 5 | 5 | 100.00 | ||
| otbn_mac_bignum_acc_err | 25.000s | 117.193us | 5 | 5 | 100.00 | ||
| otbn_urnd_err | 10.000s | 14.237us | 2 | 2 | 100.00 | ||
| V2S | illegal_bus_access | otbn_illegal_mem_acc | 9.000s | 17.431us | 5 | 5 | 100.00 |
| V2S | otbn_mem_gnt_acc_err | otbn_mem_gnt_acc_err | 9.000s | 150.346us | 2 | 2 | 100.00 |
| V2S | otbn_non_sec_partial_wipe | otbn_partial_wipe | 11.000s | 34.305us | 10 | 10 | 100.00 |
| V2S | tl_intg_err | otbn_sec_cm | 10.900m | 2.780ms | 3 | 5 | 60.00 |
| otbn_tl_intg_err | 1.017m | 390.871us | 20 | 20 | 100.00 | ||
| V2S | passthru_mem_tl_intg_err | otbn_passthru_mem_tl_intg_err | 31.000s | 136.559us | 15 | 20 | 75.00 |
| V2S | prim_fsm_check | otbn_sec_cm | 10.900m | 2.780ms | 3 | 5 | 60.00 |
| V2S | prim_count_check | otbn_sec_cm | 10.900m | 2.780ms | 3 | 5 | 60.00 |
| V2S | sec_cm_mem_scramble | otbn_smoke | 13.000s | 47.654us | 1 | 1 | 100.00 |
| V2S | sec_cm_data_mem_integrity | otbn_dmem_err | 18.000s | 686.598us | 15 | 15 | 100.00 |
| V2S | sec_cm_instruction_mem_integrity | otbn_imem_err | 12.000s | 30.949us | 10 | 10 | 100.00 |
| V2S | sec_cm_bus_integrity | otbn_tl_intg_err | 1.017m | 390.871us | 20 | 20 | 100.00 |
| V2S | sec_cm_controller_fsm_global_esc | otbn_escalate | 19.000s | 97.491us | 59 | 60 | 98.33 |
| V2S | sec_cm_controller_fsm_local_esc | otbn_imem_err | 12.000s | 30.949us | 10 | 10 | 100.00 |
| otbn_dmem_err | 18.000s | 686.598us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 11.000s | 26.720us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 9.000s | 17.431us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 10.900m | 2.780ms | 3 | 5 | 60.00 | ||
| V2S | sec_cm_controller_fsm_sparse | otbn_sec_cm | 10.900m | 2.780ms | 3 | 5 | 60.00 |
| V2S | sec_cm_scramble_key_sideload | otbn_single | 29.000s | 109.169us | 100 | 100 | 100.00 |
| V2S | sec_cm_scramble_ctrl_fsm_local_esc | otbn_imem_err | 12.000s | 30.949us | 10 | 10 | 100.00 |
| otbn_dmem_err | 18.000s | 686.598us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 11.000s | 26.720us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 9.000s | 17.431us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 10.900m | 2.780ms | 3 | 5 | 60.00 | ||
| V2S | sec_cm_scramble_ctrl_fsm_sparse | otbn_sec_cm | 10.900m | 2.780ms | 3 | 5 | 60.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_global_esc | otbn_escalate | 19.000s | 97.491us | 59 | 60 | 98.33 |
| V2S | sec_cm_start_stop_ctrl_fsm_local_esc | otbn_imem_err | 12.000s | 30.949us | 10 | 10 | 100.00 |
| otbn_dmem_err | 18.000s | 686.598us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 11.000s | 26.720us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 9.000s | 17.431us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 10.900m | 2.780ms | 3 | 5 | 60.00 | ||
| V2S | sec_cm_start_stop_ctrl_fsm_sparse | otbn_sec_cm | 10.900m | 2.780ms | 3 | 5 | 60.00 |
| V2S | sec_cm_data_reg_sw_sca | otbn_single | 29.000s | 109.169us | 100 | 100 | 100.00 |
| V2S | sec_cm_ctrl_redun | otbn_ctrl_redun | 16.000s | 46.246us | 12 | 12 | 100.00 |
| V2S | sec_cm_pc_ctrl_flow_redun | otbn_pc_ctrl_flow_redun | 9.000s | 13.032us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_bus_consistency | otbn_rnd_sec_cm | 48.000s | 165.453us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_rng_digest | otbn_rnd_sec_cm | 48.000s | 165.453us | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_integrity | otbn_rf_base_intg_err | 12.000s | 29.158us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_glitch_detect | otbn_sec_cm | 10.900m | 2.780ms | 3 | 5 | 60.00 |
| V2S | sec_cm_stack_wr_ptr_ctr_redun | otbn_sec_cm | 10.900m | 2.780ms | 3 | 5 | 60.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_integrity | otbn_rf_bignum_intg_err | 11.000s | 61.575us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_glitch_detect | otbn_sec_cm | 10.900m | 2.780ms | 3 | 5 | 60.00 |
| V2S | sec_cm_loop_stack_ctr_redun | otbn_sec_cm | 10.900m | 2.780ms | 3 | 5 | 60.00 |
| V2S | sec_cm_loop_stack_addr_integrity | otbn_stack_addr_integ_chk | 18.000s | 737.036us | 5 | 5 | 100.00 |
| V2S | sec_cm_call_stack_addr_integrity | otbn_stack_addr_integ_chk | 18.000s | 737.036us | 5 | 5 | 100.00 |
| V2S | sec_cm_start_stop_ctrl_state_consistency | otbn_sec_wipe_err | 26.000s | 513.004us | 4 | 7 | 57.14 |
| V2S | sec_cm_data_mem_sec_wipe | otbn_single | 29.000s | 109.169us | 100 | 100 | 100.00 |
| V2S | sec_cm_instruction_mem_sec_wipe | otbn_single | 29.000s | 109.169us | 100 | 100 | 100.00 |
| V2S | sec_cm_data_reg_sw_sec_wipe | otbn_single | 29.000s | 109.169us | 100 | 100 | 100.00 |
| V2S | sec_cm_write_mem_integrity | otbn_multi | 1.783m | 1.358ms | 10 | 10 | 100.00 |
| V2S | sec_cm_ctrl_flow_count | otbn_single | 29.000s | 109.169us | 100 | 100 | 100.00 |
| V2S | sec_cm_ctrl_flow_sca | otbn_single | 29.000s | 109.169us | 100 | 100 | 100.00 |
| V2S | sec_cm_data_mem_sw_noaccess | otbn_sw_no_acc | 17.000s | 126.701us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_sideload | otbn_single | 29.000s | 109.169us | 100 | 100 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | otbn_sec_cm | 10.900m | 2.780ms | 3 | 5 | 60.00 |
| V2S | TOTAL | 153 | 163 | 93.87 | |||
| V3 | stress_all_with_rand_reset | otbn_stress_all_with_rand_reset | 11.550m | 2.924ms | 3 | 10 | 30.00 |
| V3 | TOTAL | 3 | 10 | 30.00 | |||
| TOTAL | 566 | 585 | 96.75 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 99.08 | 99.64 | 96.00 | 99.71 | 93.22 | 93.39 | 100.00 | 97.72 | 100.00 |
UVM_ERROR (cip_base_vseq.sv:929) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
1.otbn_stress_all_with_rand_reset.45830351904808321225295670591408705968478751311661625631501894180521573915440
Line 280, in log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 545044480 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 545044480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.otbn_stress_all_with_rand_reset.72511465190273752092764177730177976352703663399747479478592011366403374519004
Line 217, in log /nightly/runs/scratch/master/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 337913809 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 337913809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 4 failures:
Test otbn_stress_all_with_rand_reset has 1 failures.
0.otbn_stress_all_with_rand_reset.70296712469531061622495752681374334005314837142147935670404945773846135340518
Line 251, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 818377965 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 818377965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_passthru_mem_tl_intg_err has 3 failures.
0.otbn_passthru_mem_tl_intg_err.86839988434059654434294890898470837682752497495722654781693388397427542528146
Line 82, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_passthru_mem_tl_intg_err/latest/run.log
UVM_FATAL @ 1595715 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 1595715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.otbn_passthru_mem_tl_intg_err.51224728764991722037054867667206753150201491489710900374811799543365051768803
Line 82, in log /nightly/runs/scratch/master/otbn-sim-xcelium/3.otbn_passthru_mem_tl_intg_err/latest/run.log
UVM_FATAL @ 1102934 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 1102934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 4 failures:
1.otbn_sec_wipe_err.28955225614975668274889288197399793226540419741045336243550894820670201610247
Line 131, in log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_sec_wipe_err/latest/run.log
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 46731956 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 46731956 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 46731956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.otbn_sec_wipe_err.80495357440761759715478911004327747207308620986302049855007989147886965091211
Line 112, in log /nightly/runs/scratch/master/otbn-sim-xcelium/2.otbn_sec_wipe_err/latest/run.log
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 83511716 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 83511716 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 83511716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
58.otbn_escalate.27954412847088988798504638431994670214728303072141915184637693251988169665105
Line 116, in log /nightly/runs/scratch/master/otbn-sim-xcelium/58.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 14517421 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 14517421 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 14517421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 2 failures:
0.otbn_sec_cm.110131274086988523472683278676141231289384845410846223582625570500663081527032
Line 83, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 1019873 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 1019873 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
UVM_ERROR @ 1019873 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
UVM_INFO @ 1019873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.otbn_sec_cm.37849104699048702965969127049692774749323321881251177414656158219242459523330
Line 133, in log /nightly/runs/scratch/master/otbn-sim-xcelium/3.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 454256854 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 454256854 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
UVM_ERROR @ 454256854 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
UVM_INFO @ 454256854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:
4.otbn_passthru_mem_tl_intg_err.59875940591102049925982437054735143635405583252085674629812520799960275508542
Line 82, in log /nightly/runs/scratch/master/otbn-sim-xcelium/4.otbn_passthru_mem_tl_intg_err/latest/run.log
UVM_FATAL @ 3136246 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 3136246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.otbn_passthru_mem_tl_intg_err.101672945271646792161409639500368849211505612749349224202358407776460058865415
Line 102, in log /nightly/runs/scratch/master/otbn-sim-xcelium/14.otbn_passthru_mem_tl_intg_err/latest/run.log
UVM_FATAL @ 74826232 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 74826232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job returned non-zero exit code has 1 failures:
0.otbn_multi_err.33830929293561759400354764849327245078581724968664310496485472202111315714312
Log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
make -f /nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='pushd /nightly/runs/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/runs/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --src-dir /nightly/runs/opentitan/hw/ip/otbn/dv/otbnsim/test/simple/multi /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_multi_err/latest/otbn-binaries' proj_root=/nightly/runs/opentitan run_cmd=xrun run_dir=/nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_multi_err/latest run_opts='+en_cov=1 -covmodeldir /nightly/runs/scratch/master/otbn-sim-xcelium/coverage/default/0.otbn_multi_err.2946343176 -covworkdir /nightly/runs/scratch/master/otbn-sim-xcelium/coverage -covscope default -covtest 0.otbn_multi_err.2946343176 -covoverwrite +otbn_elf_dir=/nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_multi_err/latest/otbn-binaries +cdc_instrumentation_enabled=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/runs/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/runs/scratch/master/otbn-sim-xcelium/default/xcelium.d -r tb +SVSEED=2946343176 +UVM_TESTNAME=otbn_base_test +UVM_TEST_SEQ=otbn_sequential_vseq -nowarn DSEM2009' seed=33830929293561759400354764849327245078581724968664310496485472202111315714312 sw_build_cmd=bazel sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otbn_base_test uvm_test_seq=otbn_sequential_vseq
[make]: pre_run
mkdir -p /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_multi_err/latest
cd /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_multi_err/latest && pushd /nightly/runs/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/runs/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --src-dir /nightly/runs/opentitan/hw/ip/otbn/dv/otbnsim/test/simple/multi /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_multi_err/latest/otbn-binaries
~/opentitan ~/scratch/master/otbn-sim-xcelium/0.otbn_multi_err/latest
2025/05/25 13:15:54 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
7.otbn_stress_all_with_rand_reset.77036503669745162805294111117751437163545345781304077781168370547238590442928
Line 179, in log /nightly/runs/scratch/master/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 975733059 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 975733059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---