2a67071| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 38.000s | 59.261us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 5.000s | 15.898us | 5 | 5 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 5.000s | 33.536us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 7.000s | 157.846us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 5.000s | 125.536us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 6.000s | 32.493us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 5.000s | 33.536us | 20 | 20 | 100.00 |
| pattgen_csr_aliasing | 5.000s | 125.536us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | perf | pattgen_perf | 46.750m | 600.000ms | 27 | 50 | 54.00 |
| V2 | cnt_rollover | cnt_rollover | 1.350m | 3.462ms | 50 | 50 | 100.00 |
| V2 | error | pattgen_error | 36.000s | 42.404us | 50 | 50 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 2.975h | 1.443s | 16 | 50 | 32.00 |
| V2 | alert_test | pattgen_alert_test | 36.000s | 13.932us | 50 | 50 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 5.000s | 33.617us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 7.000s | 46.487us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 7.000s | 46.487us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 5.000s | 15.898us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 5.000s | 33.536us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 5.000s | 125.536us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 5.000s | 21.072us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 5.000s | 15.898us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 5.000s | 33.536us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 5.000s | 125.536us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 5.000s | 21.072us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 283 | 340 | 83.24 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 6.000s | 120.056us | 20 | 20 | 100.00 |
| pattgen_sec_cm | 36.000s | 54.083us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 6.000s | 120.056us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 2.383m | 22.282ms | 3 | 50 | 6.00 |
| V3 | TOTAL | 3 | 50 | 6.00 | |||
| Unmapped tests | pattgen_inactive_level | 4.917m | 10.015ms | 38 | 50 | 76.00 | |
| TOTAL | 454 | 570 | 79.65 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.72 | 100.00 | 100.00 | 100.00 | 98.50 | 96.61 | -- | 100.00 | 88.15 |
UVM_ERROR (cip_base_vseq.sv:929) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 47 failures:
0.pattgen_stress_all_with_rand_reset.15570112933906966537683914411683239293462640098348505787764309150004571799069
Line 354, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8076817193 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 8076855539 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 8076855539 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 8/10
UVM_INFO @ 8077215539 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
1.pattgen_stress_all_with_rand_reset.66636796873729156549142848971377493467731617838473393602573991349157534485398
Line 206, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3447036457 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 3447064669 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3447064669 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/5
UVM_INFO @ 3447231337 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
... and 45 more failures.
Job timed out after * minutes has 26 failures:
0.pattgen_perf.26847769716626811446882811930158940529273893614395831026656618859315353304121
Log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log
Job timed out after 60 minutes
2.pattgen_perf.115646736889789861704643459612605648992566408660303395354600237101887282460797
Log /nightly/runs/scratch/master/pattgen-sim-xcelium/2.pattgen_perf/latest/run.log
Job timed out after 60 minutes
... and 11 more failures.
5.pattgen_stress_all.100474278778839478337630516784707470417197468545551668619930830938459195111349
Log /nightly/runs/scratch/master/pattgen-sim-xcelium/5.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
6.pattgen_stress_all.31445349179462315288307879695303785899303010564226284665215019081679618937468
Log /nightly/runs/scratch/master/pattgen-sim-xcelium/6.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
... and 11 more failures.
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 21 failures:
0.pattgen_stress_all.63360946280394210341393609960543409550456865462104370611477754225125035821683
Line 139, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log
UVM_ERROR @ 1076738105 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10508
2.pattgen_stress_all.71406116333551986137462758251550999109529162747832572293329537728145315481731
Line 129, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/2.pattgen_stress_all/latest/run.log
UVM_ERROR @ 84180705342 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
--------------------------------------
Name Type Size Value
--------------------------------------
exp_item pattgen_item - @10469
... and 19 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 10 failures:
1.pattgen_perf.6252418203407509245121108930811975458106623404963473124119686813677864634022
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/1.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.pattgen_perf.57073301190702432017334328141564430776464455020047236106499388136516393754096
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/3.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 3 failures:
1.pattgen_inactive_level.22914112546951967276545942367636487074329257955502289770530619501273577125503
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/1.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10012042891 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x77a89110, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
UVM_INFO @ 10012042891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
39.pattgen_inactive_level.11856796493261778486837051270340477574370374596241817025414572342501141430598
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/39.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10004764561 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x3c5f3150, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
UVM_INFO @ 10004764561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) has 2 failures:
4.pattgen_inactive_level.87598937388343139035735378608405627112796038555244717537531261086428725187797
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/4.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10027302090 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xd7b31090, Comparison=CompareOpEq, exp_data=0x0, call_count=21)
UVM_INFO @ 10027302090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
37.pattgen_inactive_level.86493939014032385628016141988157040617933408201549223581508226876089726138215
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/37.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10736655311 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xaabfda10, Comparison=CompareOpEq, exp_data=0x0, call_count=21)
UVM_INFO @ 10736655311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
0.pattgen_inactive_level.104051823390554346598108236985042302969767488712680324334247446709826561454719
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10073138909 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x9be9090, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10073138909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
9.pattgen_inactive_level.5584012696220694775782877074226259023720890229205592284327122152252313648800
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/9.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10193299555 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xe004d790, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10193299555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=24) has 1 failures:
12.pattgen_inactive_level.106800343112298813689383318910998084317336351428151584849864091895824046067228
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/12.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10057224190 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xd8206f10, Comparison=CompareOpEq, exp_data=0x0, call_count=24)
UVM_INFO @ 10057224190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=25) has 1 failures:
40.pattgen_inactive_level.78248187877675025420145148380256308415984899450175968522033847226206066074850
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/40.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10014828132 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x26cc7610, Comparison=CompareOpEq, exp_data=0x0, call_count=25)
UVM_INFO @ 10014828132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
44.pattgen_inactive_level.88384993785147701003403354747633230758157717481449350598507204274717843934283
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/44.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10043383703 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x76b53790, Comparison=CompareOpEq, exp_data=0x0, call_count=19)
UVM_INFO @ 10043383703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
46.pattgen_inactive_level.101395005118647273033093844584279858390655940313079003394986399901361445838652
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/46.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10122355530 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x9b008e10, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
UVM_INFO @ 10122355530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:
48.pattgen_inactive_level.65664372534983326530845477801602302635885243534922915254458090951091107363122
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/48.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10010123377 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x590eacd0, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
UVM_INFO @ 10010123377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---