ROM_CTRL/32KB Simulation Results

Sunday May 25 2025 00:06:37 UTC

GitHub Revision: 2a67071

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	6.100s	235.236us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	10.320s	468.785us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	9.580s	549.954us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	8.610s	169.879us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	6.870s	2.068ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	8.810s	2.063ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	9.580s	549.954us	20	20	100.00
		rom_ctrl_csr_aliasing	6.870s	2.068ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	9.590s	1.164ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	7.140s	169.316us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	7.550s	144.678us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	32.250s	11.692ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	10.090s	396.454us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	7.810s	164.901us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	10.800s	313.671us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	10.800s	313.671us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	10.320s	468.785us	5	5	100.00
		rom_ctrl_csr_rw	9.580s	549.954us	20	20	100.00
		rom_ctrl_csr_aliasing	6.870s	2.068ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	8.780s	631.735us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	10.320s	468.785us	5	5	100.00
		rom_ctrl_csr_rw	9.580s	549.954us	20	20	100.00
		rom_ctrl_csr_aliasing	6.870s	2.068ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	8.780s	631.735us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	2.154m	10.565ms	16	20	80.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	39.740s	6.714ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.762m	1.371ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.177m	529.900us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.762m	1.371ms	5	5	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	4.762m	1.371ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.154m	10.565ms	16	20	80.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.154m	10.565ms	16	20	80.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.154m	10.565ms	16	20	80.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.154m	10.565ms	16	20	80.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.154m	10.565ms	16	20	80.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.762m	1.371ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.762m	1.371ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	6.100s	235.236us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	6.100s	235.236us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	6.100s	235.236us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.177m	529.900us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.154m	10.565ms	16	20	80.00
		rom_ctrl_kmac_err_chk	10.090s	396.454us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	2.154m	10.565ms	16	20	80.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.154m	10.565ms	16	20	80.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	2.154m	10.565ms	16	20	80.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	39.740s	6.714ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.762m	1.371ms	5	5	100.00
V2S		TOTAL			61	65	93.85
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	8.683m	62.344ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			262	266	98.50

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.67	100.00	99.41	100.00	100.00	100.00	98.97	99.28

Failure Buckets

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 3 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 3 failures.

    • 3.rom_ctrl_corrupt_sig_fatal_chk.93207324207942286301353182015514445302559330018025967864449978465589153080530
      Line 87, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 434516934 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 434516934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 14.rom_ctrl_corrupt_sig_fatal_chk.52418791333039073097750433713104613941653844048158369871401145259618588618464
      Line 75, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 284462484 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 284462484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• Offending '(counter_lnt -> kmac_rom_vld_o)' has 1 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 1.rom_ctrl_corrupt_sig_fatal_chk.43561487428664394789140640224009812911433234345669747175064383067532237097086
      Line 97, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

            Offending '(counter_lnt -> kmac_rom_vld_o)'
        UVM_ERROR @ 1102021807 ps: (rom_ctrl_fsm.sv:353) [ASSERT FAILED] CounterLntImpliesKmacRomVldO_A
        UVM_INFO @ 1102021807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---