RV_TIMER Simulation Results

Sunday May 25 2025 00:06:37 UTC

GitHub Revision: 2a67071

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.980s	48.174us	20	20	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.980s	58.701us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	2.300s	13.497us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.900s	557.570us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	2.340s	37.029us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	2.480s	119.039us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	2.300s	13.497us	20	20	100.00
		rv_timer_csr_aliasing	2.340s	37.029us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	random_reset	rv_timer_random_reset	18.520s	15.381ms	20	20	100.00
V2	disabled	rv_timer_disabled	5.190s	2.081ms	20	20	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	12.276m	2.110s	10	10	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	12.276m	2.110s	10	10	100.00
V2	stress	rv_timer_stress_all	17.090s	7.586ms	20	20	100.00
V2	alert_test	rv_timer_alert_test	2.240s	17.731us	50	50	100.00
V2	intr_test	rv_timer_intr_test	2.140s	28.868us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	4.180s	491.766us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	4.180s	491.766us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.980s	58.701us	5	5	100.00
		rv_timer_csr_rw	2.300s	13.497us	20	20	100.00
		rv_timer_csr_aliasing	2.340s	37.029us	5	5	100.00
		rv_timer_same_csr_outstanding	2.180s	31.940us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.980s	58.701us	5	5	100.00
		rv_timer_csr_rw	2.300s	13.497us	20	20	100.00
		rv_timer_csr_aliasing	2.340s	37.029us	5	5	100.00
		rv_timer_same_csr_outstanding	2.180s	31.940us	20	20	100.00
V2		TOTAL			210	210	100.00
V2S	tl_intg_err	rv_timer_sec_cm	2.190s	89.260us	5	5	100.00
		rv_timer_tl_intg_err	2.610s	135.326us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.610s	135.326us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	47.290s	7.498ms	20	20	100.00
V3		TOTAL			20	20	100.00
	Unmapped tests	rv_timer_min	1.950s	35.981us	10	10	100.00
		rv_timer_max	1.900s	32.211us	10	10	100.00
		TOTAL			350	350	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
100.00	100.00	100.00	100.00	--	100.00	100.00	100.00