SPI_DEVICE/1R1W Simulation Results

Sunday May 25 2025 00:06:37 UTC

GitHub Revision: 2a67071

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	8.797m	811.569ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.930s	187.231us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	4.260s	327.528us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	31.120s	12.246ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	19.490s	625.535us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.790s	1.945ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	4.260s	327.528us	20	20	100.00
		spi_device_csr_aliasing	19.490s	625.535us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	2.230s	41.735us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.210s	80.052us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	2.500s	76.005us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	2.340s	1.772us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	1.810s	5.601us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	6.590s	255.206us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	6.590s	255.206us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	28.710s	10.268ms	50	50	100.00
		spi_device_tpm_sts_read	2.660s	89.187us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	38.380s	29.130ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	39.320s	41.979ms	50	50	100.00
		spi_device_flash_all	5.295m	57.810ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	34.690s	26.168ms	50	50	100.00
		spi_device_flash_all	5.295m	57.810ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	34.690s	26.168ms	50	50	100.00
		spi_device_flash_all	5.295m	57.810ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	5.295m	57.810ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	33.060s	13.461ms	50	50	100.00
		spi_device_flash_all	5.295m	57.810ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	33.060s	13.461ms	50	50	100.00
		spi_device_flash_all	5.295m	57.810ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	33.060s	13.461ms	50	50	100.00
		spi_device_flash_all	5.295m	57.810ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	33.060s	13.461ms	50	50	100.00
		spi_device_flash_all	5.295m	57.810ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	33.060s	13.461ms	50	50	100.00
		spi_device_flash_all	5.295m	57.810ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	30.560s	12.246ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.871m	39.012ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.871m	39.012ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.871m	39.012ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	51.410s	32.058ms	50	50	100.00
		spi_device_read_buffer_direct	21.940s	1.670ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.871m	39.012ms	50	50	100.00
		spi_device_flash_all	5.295m	57.810ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	5.295m	57.810ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	5.295m	57.810ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	19.790s	9.325ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	19.790s	9.325ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	8.797m	811.569ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	6.749m	106.750ms	50	50	100.00
V2	stress_all	spi_device_stress_all	9.303m	161.277ms	50	50	100.00
V2	alert_test	spi_device_alert_test	2.450s	16.408us	50	50	100.00
V2	intr_test	spi_device_intr_test	2.430s	54.397us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.060s	208.833us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.060s	208.833us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.930s	187.231us	5	5	100.00
		spi_device_csr_rw	4.260s	327.528us	20	20	100.00
		spi_device_csr_aliasing	19.490s	625.535us	5	5	100.00
		spi_device_same_csr_outstanding	4.970s	701.960us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.930s	187.231us	5	5	100.00
		spi_device_csr_rw	4.260s	327.528us	20	20	100.00
		spi_device_csr_aliasing	19.490s	625.535us	5	5	100.00
		spi_device_same_csr_outstanding	4.970s	701.960us	20	20	100.00
V2		TOTAL			940	961	97.81
V2S	tl_intg_err	spi_device_sec_cm	2.570s	367.184us	5	5	100.00
		spi_device_tl_intg_err	19.980s	10.030ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	19.980s	10.030ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	4.132m	141.846ms	49	50	98.00
		TOTAL			1129	1151	98.09

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.54	98.98	96.55	83.54	89.36	98.39	95.66	99.26

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:

  • Test spi_device_mem_parity has 20 failures.

    • 0.spi_device_mem_parity.114970382343446933091550518529407281599364846073455846926610895858951497179282
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   3722522 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[89])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   3722522 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   3722522 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[985])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • 1.spi_device_mem_parity.115242000395163429718224485726369650436626702414483907525980717624279108064410
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   3416476 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[21])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   3416476 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   3416476 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[917])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • ... and 18 more failures.

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.9692584495833111861428725545188679595932700404214847084091406211864284229704
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   3171325 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7bcdf7 [11110111100110111110111] vs 0x0 [0])
        UVM_ERROR @   3226325 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2e97e8 [1011101001011111101000] vs 0x0 [0])
        UVM_ERROR @   3314325 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x471b1a [10001110001101100011010] vs 0x0 [0])
        UVM_ERROR @   3358325 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x262370 [1001100010001101110000] vs 0x0 [0])
        UVM_ERROR @   3423325 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x872b05 [100001110010101100000101] vs 0x0 [0])
      

• UVM_ERROR (spi_device_pass_base_vseq.sv:705) [spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:

  • Test spi_device_flash_mode_ignore_cmds has 1 failures.

    • 36.spi_device_flash_mode_ignore_cmds.47137352926625062962415049982040226705103084715083589795362864999108483041599
      Line 85, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/36.spi_device_flash_mode_ignore_cmds/latest/run.log

        UVM_ERROR @ 1440324845 ps: (spi_device_pass_base_vseq.sv:705) [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
        tl_ul_fuzzy_flash_status_q[i] = 0xecf6f0
        tl_ul_fuzzy_flash_status_q[i] = 0x883d48
        UVM_INFO @ 1533915345 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 3/6
        UVM_INFO @ 1533915345 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 4/6