SPI_DEVICE/2P Simulation Results

Sunday May 25 2025 00:06:37 UTC

GitHub Revision: `2a67071`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	11.317m	418.869ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.940s	22.288us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	4.250s	434.814us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	32.130s	5.530ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	19.310s	316.290us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.920s	53.608us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	4.250s	434.814us	20	20	100.00
		spi_device_csr_aliasing	19.310s	316.290us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	2.310s	13.238us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.820s	218.368us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	2.430s	57.923us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	2.720s	130.044us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	1.820s	27.253us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	9.130s	736.243us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	9.130s	736.243us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	27.760s	15.569ms	50	50	100.00
		spi_device_tpm_sts_read	2.860s	490.235us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	56.270s	12.545ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	24.850s	16.939ms	50	50	100.00
		spi_device_flash_all	7.709m	82.938ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	28.110s	4.925ms	50	50	100.00
		spi_device_flash_all	7.709m	82.938ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	28.110s	4.925ms	50	50	100.00
		spi_device_flash_all	7.709m	82.938ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.709m	82.938ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	30.180s	53.989ms	50	50	100.00
		spi_device_flash_all	7.709m	82.938ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	30.180s	53.989ms	50	50	100.00
		spi_device_flash_all	7.709m	82.938ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	30.180s	53.989ms	50	50	100.00
		spi_device_flash_all	7.709m	82.938ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	30.180s	53.989ms	50	50	100.00
		spi_device_flash_all	7.709m	82.938ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	30.180s	53.989ms	50	50	100.00
		spi_device_flash_all	7.709m	82.938ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	22.130s	29.014ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.853m	64.864ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.853m	64.864ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.853m	64.864ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	56.780s	9.772ms	50	50	100.00
		spi_device_read_buffer_direct	20.080s	1.638ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.853m	64.864ms	50	50	100.00
		spi_device_flash_all	7.709m	82.938ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.709m	82.938ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.709m	82.938ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	27.910s	6.255ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	27.910s	6.255ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.317m	418.869ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	8.871m	69.373ms	50	50	100.00
V2	stress_all	spi_device_stress_all	9.308m	103.116ms	50	50	100.00
V2	alert_test	spi_device_alert_test	2.410s	11.763us	50	50	100.00
V2	intr_test	spi_device_intr_test	2.510s	18.530us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.630s	203.116us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.630s	203.116us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.940s	22.288us	5	5	100.00
		spi_device_csr_rw	4.250s	434.814us	20	20	100.00
		spi_device_csr_aliasing	19.310s	316.290us	5	5	100.00
		spi_device_same_csr_outstanding	5.850s	250.127us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.940s	22.288us	5	5	100.00
		spi_device_csr_rw	4.250s	434.814us	20	20	100.00
		spi_device_csr_aliasing	19.310s	316.290us	5	5	100.00
		spi_device_same_csr_outstanding	5.850s	250.127us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	2.940s	1.168ms	5	5	100.00
		spi_device_tl_intg_err	19.900s	6.048ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	19.900s	6.048ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	17.902m	1.500s	48	50	96.00
		TOTAL			1149	1151	99.83

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.17	99.04	96.65	87.74	89.36	98.47	95.65	99.26

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 18.spi_device_flash_mode_ignore_cmds.45713430628005475359669816650450636667854356759668219663543714273833280937841
    Line 76, in log /nightly/runs/scratch/master/spi_device_2p-sim-vcs/18.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (spi_device_scoreboard.sv:2799) [scoreboard] Check failed upload_cmd_q.size == * (* [*] vs * [*]) has 1 failures:

Test spi_device_flash_mode_ignore_cmds has 1 failures.

40.spi_device_flash_mode_ignore_cmds.46859541758861641384085495272687566878601492226112157061051667399367408991701
Line 126, in log /nightly/runs/scratch/master/spi_device_2p-sim-vcs/40.spi_device_flash_mode_ignore_cmds/latest/run.log

  UVM_ERROR @ 3469422721 ps: (spi_device_scoreboard.sv:2799) [uvm_test_top.env.scoreboard] Check failed upload_cmd_q.size == 0 (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 3469422721 ps: (spi_device_scoreboard.sv:2800) [uvm_test_top.env.scoreboard] Check failed upload_addr_q.size == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 3469422721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---