SPI_HOST Simulation Results

Sunday May 25 2025 00:06:37 UTC

GitHub Revision: 2a67071

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	1.967m	9.556ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	5.000s	99.237us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	5.000s	73.464us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	8.000s	163.136us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	5.000s	66.082us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	5.000s	25.573us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	5.000s	73.464us	20	20	100.00
		spi_host_csr_aliasing	5.000s	66.082us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	5.000s	32.623us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	5.000s	18.618us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	5.000s	26.868us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	24.000s	887.719us	50	50	100.00
		spi_host_error_cmd	5.000s	20.809us	50	50	100.00
		spi_host_event	11.233m	97.895ms	50	50	100.00
V2	clock_rate	spi_host_speed	13.000s	665.686us	50	50	100.00
V2	speed	spi_host_speed	13.000s	665.686us	50	50	100.00
V2	chip_select_timing	spi_host_speed	13.000s	665.686us	50	50	100.00
V2	sw_reset	spi_host_sw_reset	1.133m	3.776ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	5.000s	47.906us	50	50	100.00
V2	cpol_cpha	spi_host_speed	13.000s	665.686us	50	50	100.00
V2	full_cycle	spi_host_speed	13.000s	665.686us	50	50	100.00
V2	duplex	spi_host_smoke	1.967m	9.556ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	1.967m	9.556ms	50	50	100.00
V2	stress_all	spi_host_stress_all	2.317m	2.816ms	50	50	100.00
V2	spien	spi_host_spien	2.917m	4.581ms	50	50	100.00
V2	stall	spi_host_status_stall	31.717m	52.370ms	50	50	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	22.000s	962.103us	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	24.000s	887.719us	50	50	100.00
V2	alert_test	spi_host_alert_test	5.000s	119.343us	50	50	100.00
V2	intr_test	spi_host_intr_test	5.000s	162.874us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	7.000s	222.777us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	7.000s	222.777us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	5.000s	99.237us	5	5	100.00
		spi_host_csr_rw	5.000s	73.464us	20	20	100.00
		spi_host_csr_aliasing	5.000s	66.082us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	69.498us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	5.000s	99.237us	5	5	100.00
		spi_host_csr_rw	5.000s	73.464us	20	20	100.00
		spi_host_csr_aliasing	5.000s	66.082us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	69.498us	20	20	100.00
V2		TOTAL			690	690	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	6.000s	95.799us	20	20	100.00
		spi_host_sec_cm	5.000s	208.196us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	6.000s	95.799us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	11.783m	91.606ms	10	10	100.00
		TOTAL			840	840	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.26	96.78	93.27	98.69	94.36	88.02	100.00	97.27	90.42