SRAM_CTRL/MAIN Simulation Results

Sunday May 25 2025 00:06:37 UTC

GitHub Revision: 2a67071

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.339m	820.233us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.160s	16.319us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.240s	42.031us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.420s	122.237us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.220s	69.849us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	6.710s	1.169ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.240s	42.031us	20	20	100.00
		sram_ctrl_csr_aliasing	2.220s	69.849us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.313m	43.099ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.056m	33.402ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	24.985m	70.952ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.355m	9.664ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	38.563m	303.609ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	23.336m	95.645ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.850m	74.243ms	50	50	100.00
V2	executable	sram_ctrl_executable	25.323m	134.885ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.833m	2.163ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.237m	23.942ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.553m	815.394us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.653m	817.077us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.762m	1.057ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	21.400m	186.432ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	7.010s	2.235ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.914h	304.235ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.240s	183.003us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	6.710s	561.754us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	6.710s	561.754us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.160s	16.319us	5	5	100.00
		sram_ctrl_csr_rw	2.240s	42.031us	20	20	100.00
		sram_ctrl_csr_aliasing	2.220s	69.849us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.280s	16.962us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.160s	16.319us	5	5	100.00
		sram_ctrl_csr_rw	2.240s	42.031us	20	20	100.00
		sram_ctrl_csr_aliasing	2.220s	69.849us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.280s	16.962us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	54.540s	14.131ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.070s	3.824us	0	5	0.00
		sram_ctrl_tl_intg_err	5.450s	823.599us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.070s	3.824us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	5.450s	823.599us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	21.400m	186.432ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	21.400m	186.432ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.240s	42.031us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	25.323m	134.885ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	25.323m	134.885ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	25.323m	134.885ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.850m	74.243ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	12.030s	6.644ms	45	50	90.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	54.540s	14.131ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	11.320s	4.709ms	36	50	72.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.339m	820.233us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.339m	820.233us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	25.323m	134.885ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.070s	3.824us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.850m	74.243ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.070s	3.824us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.070s	3.824us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.339m	820.233us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.070s	3.824us	0	5	0.00
V2S		TOTAL			121	145	83.45
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.865m	3.056ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1166	1190	97.98

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.06	99.29	93.01	85.18	100.00	98.03	98.59	98.33

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 14 failures:

  • Test sram_ctrl_readback_err has 14 failures.

    • 7.sram_ctrl_readback_err.18140761742546416291350908809823533054661147475062473938846623802129164655462
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/7.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 697317446 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0xf) != exp (0x42)
        UVM_INFO @ 697317446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 9.sram_ctrl_readback_err.24024506936200578920520264051445281336847845523791375958896398162900426576016
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/9.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 664639202 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x78) != exp (0x34)
        UVM_INFO @ 664639202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 12 more failures.

• Offending 'reqfifo_rvalid' has 5 failures:

  • Test sram_ctrl_mubi_enc_err has 5 failures.

    • 4.sram_ctrl_mubi_enc_err.49868068111461145869308901668468742687346289001788100788386264118689135950314
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 2741325693 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 2741325693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 13.sram_ctrl_mubi_enc_err.60070674357883726048108821949649434197585601123073521761170589854358626793157
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/13.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 691350028 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 691350028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 3 failures:

  • Test sram_ctrl_sec_cm has 3 failures.

    • 0.sram_ctrl_sec_cm.42861604877614348707472950820222661820710396672232823446636791741733926320449
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  18905627 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  18905627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.sram_ctrl_sec_cm.81585045934421830681603568751935984116826219025145907638783315549081416718294
      Line 98, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   9928603 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   9928603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• Offending 'pend_req[d2h.d_source].pend' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 2.sram_ctrl_sec_cm.44934441842861434356431289307230665457218617680911682973535056312834485633952
      Line 96, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

            Offending 'pend_req[d2h.d_source].pend'
        UVM_ERROR @   3824395 ps: (tlul_assert.sv:276) [ASSERT FAILED] respMustHaveReq_A
        UVM_INFO @   3824395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 4.sram_ctrl_sec_cm.95829350538148453220816539557582786939140156182265375041510760520410051515461
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @  11594871 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  11594871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---