SRAM_CTRL/RET Simulation Results

Sunday May 25 2025 00:06:37 UTC

GitHub Revision: 2a67071

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.686m	149.806us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.110s	14.523us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.050s	23.744us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.610s	89.154us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.060s	18.604us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.400s	41.496us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.050s	23.744us	20	20	100.00
		sram_ctrl_csr_aliasing	2.060s	18.604us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	14.000s	2.128ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	8.120s	402.726us	50	50	100.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	21.107m	4.304ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.085m	7.447ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.544m	6.316ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	19.118m	16.188ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	12.650s	3.991ms	50	50	100.00
V2	executable	sram_ctrl_executable	21.966m	54.152ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.872m	2.636ms	50	50	100.00
		sram_ctrl_partial_access_b2b	12.404m	552.234ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.599m	594.314us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.352m	199.017us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.698m	614.035us	50	50	100.00
V2	regwen	sram_ctrl_regwen	20.797m	23.721ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.490s	26.686us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.338h	83.251ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.190s	14.712us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	6.340s	796.914us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	6.340s	796.914us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.110s	14.523us	5	5	100.00
		sram_ctrl_csr_rw	2.050s	23.744us	20	20	100.00
		sram_ctrl_csr_aliasing	2.060s	18.604us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.210s	81.381us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.110s	14.523us	5	5	100.00
		sram_ctrl_csr_rw	2.050s	23.744us	20	20	100.00
		sram_ctrl_csr_aliasing	2.060s	18.604us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.210s	81.381us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	5.360s	447.140us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.180s	11.711us	0	5	0.00
		sram_ctrl_tl_intg_err	3.870s	175.913us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.180s	11.711us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.870s	175.913us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	20.797m	23.721ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	20.797m	23.721ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.050s	23.744us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	21.966m	54.152ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	21.966m	54.152ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	21.966m	54.152ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	12.650s	3.991ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.710s	175.429us	41	50	82.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	5.360s	447.140us	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.570s	150.654us	32	50	64.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.686m	149.806us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.686m	149.806us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	21.966m	54.152ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.180s	11.711us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	12.650s	3.991ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.180s	11.711us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.180s	11.711us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.686m	149.806us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.180s	11.711us	0	5	0.00
V2S		TOTAL			113	145	77.93
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	7.679m	1.653ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1155	1190	97.06

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.06	99.26	93.01	85.10	100.00	97.99	98.58	98.52

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 18 failures:

  • Test sram_ctrl_readback_err has 18 failures.

    • 0.sram_ctrl_readback_err.32363915104463297467961718968206760550032116627196269421124688405820788687684
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  54038725 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x3b) != exp (0x31)
        UVM_INFO @  54038725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.sram_ctrl_readback_err.104544781483890395409991996681159501688399204188826086885270950056217689029042
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  28116513 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x42) != exp (0x13)
        UVM_INFO @  28116513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 16 more failures.

• Offending 'reqfifo_rvalid' has 9 failures:

  • Test sram_ctrl_mubi_enc_err has 9 failures.

    • 8.sram_ctrl_mubi_enc_err.29847978168066372011539564419801049783748469978295820033707949554853405930290
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/8.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  32085486 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  32085486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 10.sram_ctrl_mubi_enc_err.24157819655051486035210377420473356445599814891023522469809291820609288007532
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/10.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 111720280 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 111720280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 7 more failures.

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 3 failures:

  • Test sram_ctrl_sec_cm has 3 failures.

    • 0.sram_ctrl_sec_cm.55096251297950225055444400976787853212449798030188817074461519678777429691613
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   4693563 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   4693563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.sram_ctrl_sec_cm.65962571284249373397148418840672781568664602440954705406478547806481973312259
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  11710698 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  11710698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• Offending '(depth_o <= *'(Depth))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 1.sram_ctrl_sec_cm.31421877660865522933820281349488284309917156482169877609468893958990560493731
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   5982652 ps: (prim_fifo_sync.sv:209) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   5982652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 2.sram_ctrl_sec_cm.99516467649568718371528683444876268629033274766248885337417004750829476920463
      Line 101, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   7986807 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   7986807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 2.sram_ctrl_csr_mem_rw_with_rand_reset.16715434453265904311366183974717389297440820178402170492817162559062558561068
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  94206607 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
        UVM_INFO @  94206607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 19.sram_ctrl_csr_mem_rw_with_rand_reset.2527146507512973435451557264612880039035204693178273798742895518133494209824
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  98529064 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (3 [0x3] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
        UVM_INFO @  98529064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:928) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test sram_ctrl_stress_all_with_rand_reset has 1 failures.

    • 31.sram_ctrl_stress_all_with_rand_reset.57358413025304881524581744277873514749196853217917059799276214845098788603727
      Line 296, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/31.sram_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10931072890 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 75000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 10931072890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---