UART Simulation Results

Sunday May 25 2025 00:06:37 UTC

GitHub Revision: 2a67071

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	37.990s	5.827ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	2.320s	61.401us	5	5	100.00
V1	csr_rw	uart_csr_rw	2.290s	16.846us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	3.910s	1.191ms	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	2.560s	32.631us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	2.640s	521.142us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	2.290s	16.846us	20	20	100.00
		uart_csr_aliasing	2.560s	32.631us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	6.337m	134.791ms	50	50	100.00
V2	parity	uart_smoke	37.990s	5.827ms	50	50	100.00
		uart_tx_rx	6.337m	134.791ms	50	50	100.00
V2	parity_error	uart_intr	7.281m	271.016ms	50	50	100.00
		uart_rx_parity_err	8.107m	206.088ms	49	50	98.00
V2	watermark	uart_tx_rx	6.337m	134.791ms	50	50	100.00
		uart_intr	7.281m	271.016ms	50	50	100.00
V2	fifo_full	uart_fifo_full	5.719m	158.674ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	4.698m	227.564ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	8.768m	166.002ms	299	300	99.67
V2	rx_frame_err	uart_intr	7.281m	271.016ms	50	50	100.00
V2	rx_break_err	uart_intr	7.281m	271.016ms	50	50	100.00
V2	rx_timeout	uart_intr	7.281m	271.016ms	50	50	100.00
V2	perf	uart_perf	16.468m	19.070ms	50	50	100.00
V2	sys_loopback	uart_loopback	35.620s	10.648ms	50	50	100.00
V2	line_loopback	uart_loopback	35.620s	10.648ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	3.522m	236.741ms	49	50	98.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.988m	76.829ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	24.890s	6.014ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.176m	7.346ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	15.177m	131.036ms	50	50	100.00
V2	stress_all	uart_stress_all	32.149m	686.537ms	49	50	98.00
V2	alert_test	uart_alert_test	2.190s	15.934us	50	50	100.00
V2	intr_test	uart_intr_test	2.470s	15.964us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	3.820s	175.009us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	3.820s	175.009us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	2.320s	61.401us	5	5	100.00
		uart_csr_rw	2.290s	16.846us	20	20	100.00
		uart_csr_aliasing	2.560s	32.631us	5	5	100.00
		uart_same_csr_outstanding	2.500s	59.536us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	2.320s	61.401us	5	5	100.00
		uart_csr_rw	2.290s	16.846us	20	20	100.00
		uart_csr_aliasing	2.560s	32.631us	5	5	100.00
		uart_same_csr_outstanding	2.500s	59.536us	20	20	100.00
V2		TOTAL			1086	1090	99.63
V2S	tl_intg_err	uart_sec_cm	2.620s	131.726us	5	5	100.00
		uart_tl_intg_err	3.130s	118.223us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	3.130s	118.223us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	1.928m	27.032ms	98	100	98.00
V3		TOTAL			98	100	98.00
		TOTAL			1314	1320	99.55

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.77	99.17	98.25	91.55	--	98.14	100.00	99.50

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty has 3 failures:

  • Test uart_stress_all has 1 failures.

    • 16.uart_stress_all.99833197597028663420403790606959270014715616858819641914013272913218881758439
      Line 80, in log /nightly/runs/scratch/master/uart-sim-vcs/16.uart_stress_all/latest/run.log

        UVM_ERROR @ 148022711834 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_ERROR @ 148022711834 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxWatermark
        UVM_INFO @ 148371791014 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_parity_err_vseq] finished run 1/9
        UVM_INFO @ 158190075034 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_parity_err_vseq] finished run 2/9
        UVM_INFO @ 158309938524 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_parity_err_vseq] finished run 3/9
      

  • Test uart_noise_filter has 1 failures.

    • 25.uart_noise_filter.22007405213229700925590182898287858553568925483286844797043560926418032103496
      Line 69, in log /nightly/runs/scratch/master/uart-sim-vcs/25.uart_noise_filter/latest/run.log

        UVM_ERROR @   3702678 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 22367115691 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 1/8
        UVM_INFO @ 51644272249 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 2/8
        UVM_INFO @ 82217199741 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 3/8
        UVM_INFO @ 93473061311 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 4/8
      

  • Test uart_fifo_reset has 1 failures.

    • 73.uart_fifo_reset.95401233088984121568768183490719625572916086262258559514937744396668424301725
      Line 69, in log /nightly/runs/scratch/master/uart-sim-vcs/73.uart_fifo_reset/latest/run.log

        UVM_ERROR @   6011945 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 36591221291 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/7
        UVM_INFO @ 37644063047 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/7
        UVM_INFO @ 70045280588 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/7
        UVM_INFO @ 89868980843 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/7
      

• UVM_ERROR (cip_base_vseq.sv:832) [uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:

  • Test uart_stress_all_with_rand_reset has 2 failures.

    • 6.uart_stress_all_with_rand_reset.44087654361153150634879488860672796391850169247405997351380324180174721062773
      Line 149, in log /nightly/runs/scratch/master/uart-sim-vcs/6.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 745610833 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 745610833 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Issuing reset for run 10/10
        UVM_INFO @ 745713923 ps: (cip_base_vseq.sv:856) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Stress w/ reset is done for run 10/10
      

    • 39.uart_stress_all_with_rand_reset.115469668083832226499135821482779271449124818434740961423555055454577288293639
      Line 79, in log /nightly/runs/scratch/master/uart-sim-vcs/39.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7992395991 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 7992395991 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Issuing reset for run 1/10
        UVM_INFO @ 7992729324 ps: (cip_base_vseq.sv:856) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Stress w/ reset is done for run 1/10
      

• UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxWatermark has 1 failures:

  • Test uart_rx_parity_err has 1 failures.

    • 30.uart_rx_parity_err.73953052308884238545444061937452727749716595443871671188727715907712759158279
      Line 71, in log /nightly/runs/scratch/master/uart-sim-vcs/30.uart_rx_parity_err/latest/run.log

        UVM_ERROR @ 20793117265 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxWatermark
        UVM_INFO @ 55509717744 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_parity_err_vseq] finished run 3/8
        UVM_INFO @ 59472823726 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_parity_err_vseq] finished run 4/8
        UVM_INFO @ 69191436795 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_parity_err_vseq] finished run 5/8
        UVM_INFO @ 69375401015 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_parity_err_vseq] finished run 6/8