ADC_CTRL Simulation Results

Sunday June 01 2025 00:07:48 UTC

GitHub Revision: `a4c7f98`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	24.600s	5.920ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	5.920s	1.234ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	4.030s	447.662us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	2.201m	44.582ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	7.180s	1.095ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	4.060s	488.057us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	4.030s	447.662us	20	20	100.00
		adc_ctrl_csr_aliasing	7.180s	1.095ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.116m	494.113ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	21.075m	486.127ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	21.677m	499.605ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	17.826m	486.647ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	24.408m	611.769ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	30.079m	604.285ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	22.947m	529.054ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	21.346m	537.064ms	34	50	68.00
V2	poweron_counter	adc_ctrl_poweron_counter	20.830s	5.458ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	2.135m	35.453ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	5.409m	123.545ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	42.790m	3.293s	48	50	96.00
V2	alert_test	adc_ctrl_alert_test	3.740s	527.384us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	3.630s	489.801us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	5.220s	556.221us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	5.220s	556.221us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	5.920s	1.234ms	5	5	100.00
		adc_ctrl_csr_rw	4.030s	447.662us	20	20	100.00
		adc_ctrl_csr_aliasing	7.180s	1.095ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	16.290s	4.439ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	5.920s	1.234ms	5	5	100.00
		adc_ctrl_csr_rw	4.030s	447.662us	20	20	100.00
		adc_ctrl_csr_aliasing	7.180s	1.095ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	16.290s	4.439ms	20	20	100.00
V2		TOTAL			722	740	97.57
V2S	tl_intg_err	adc_ctrl_sec_cm	29.900s	7.765ms	5	5	100.00
		adc_ctrl_tl_intg_err	33.910s	8.550ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	33.910s	8.550ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	49.770m	10.000s	44	50	88.00
V3		TOTAL			44	50	88.00
		TOTAL			896	920	97.39

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.40	99.05	95.99	100.00	100.00	98.64	97.57	90.56

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 17 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 5 failures.
  - 0.adc_ctrl_stress_all_with_rand_reset.81925412562469038638486943371933384476667481597177927880889493756692220110897
    Line 181, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.adc_ctrl_stress_all_with_rand_reset.89118976408531278116197974269558851644770203246492559832729803731027442442841
    Line 173, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
- Test adc_ctrl_clock_gating has 11 failures.
  - 2.adc_ctrl_clock_gating.4179794915985603299185146650958541662794866355503467333825176467211325963238
    Line 163, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/2.adc_ctrl_clock_gating/latest/run.log
```
  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.adc_ctrl_clock_gating.83226250212047322074335743307377297222163188271171280725096931864374430316946
    Line 163, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/9.adc_ctrl_clock_gating/latest/run.log
```
  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 9 more failures.
- Test adc_ctrl_stress_all has 1 failures.
  - 27.adc_ctrl_stress_all.73391494040238183395058734344994039015774560705815386526683606257343522987076
    Line 279, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/27.adc_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:251) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 7 failures:

Test adc_ctrl_clock_gating has 5 failures.

5.adc_ctrl_clock_gating.78729198174112401584887496354290291755446015684973273004440361798415229885476
Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/5.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 1482198927 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 1482198927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.adc_ctrl_clock_gating.51118346053686273690890852210283685969441156762674000154304432846955141873767
Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/8.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 3513240382 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 3513240382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test adc_ctrl_stress_all has 1 failures.

6.adc_ctrl_stress_all.2714401605373589998754490839039020857224573394934203882577634874434178973562
Line 147, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/6.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 2250228542 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 2250228542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
- 8.adc_ctrl_stress_all_with_rand_reset.70532543074979679738130941620000102975386330866597614991640716870588811596246
  Line 159, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/8.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1365332184 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 1365332184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```