AES/MASKED Simulation Results

Sunday June 01 2025 00:07:48 UTC

GitHub Revision: `a4c7f98`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	66.021us	1	1	100.00
V1	smoke	aes_smoke	10.000s	490.698us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	84.179us	5	5	100.00
V1	csr_rw	aes_csr_rw	6.000s	77.468us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	3.718ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	212.589us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	6.000s	76.032us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	6.000s	77.468us	20	20	100.00
		aes_csr_aliasing	6.000s	212.589us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	10.000s	490.698us	50	50	100.00
		aes_config_error	43.000s	4.201ms	50	50	100.00
		aes_stress	16.000s	665.628us	50	50	100.00
V2	key_length	aes_smoke	10.000s	490.698us	50	50	100.00
		aes_config_error	43.000s	4.201ms	50	50	100.00
		aes_stress	16.000s	665.628us	50	50	100.00
V2	back2back	aes_stress	16.000s	665.628us	50	50	100.00
		aes_b2b	35.000s	713.278us	50	50	100.00
V2	backpressure	aes_stress	16.000s	665.628us	50	50	100.00
V2	multi_message	aes_smoke	10.000s	490.698us	50	50	100.00
		aes_config_error	43.000s	4.201ms	50	50	100.00
		aes_stress	16.000s	665.628us	50	50	100.00
		aes_alert_reset	17.000s	863.371us	50	50	100.00
V2	failure_test	aes_man_cfg_err	6.000s	94.965us	50	50	100.00
		aes_config_error	43.000s	4.201ms	50	50	100.00
		aes_alert_reset	17.000s	863.371us	50	50	100.00
V2	trigger_clear_test	aes_clear	12.000s	370.086us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	10.000s	1.624ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	17.000s	863.371us	50	50	100.00
V2	stress	aes_stress	16.000s	665.628us	50	50	100.00
V2	sideload	aes_stress	16.000s	665.628us	50	50	100.00
		aes_sideload	16.000s	659.653us	50	50	100.00
V2	deinitialization	aes_deinit	9.000s	297.958us	50	50	100.00
V2	stress_all	aes_stress_all	1.217m	3.616ms	10	10	100.00
V2	alert_test	aes_alert_test	6.000s	208.551us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	300.584us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	300.584us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	84.179us	5	5	100.00
		aes_csr_rw	6.000s	77.468us	20	20	100.00
		aes_csr_aliasing	6.000s	212.589us	5	5	100.00
		aes_same_csr_outstanding	6.000s	870.908us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	84.179us	5	5	100.00
		aes_csr_rw	6.000s	77.468us	20	20	100.00
		aes_csr_aliasing	6.000s	212.589us	5	5	100.00
		aes_same_csr_outstanding	6.000s	870.908us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	27.000s	5.436ms	50	50	100.00
V2S	fault_inject	aes_fi	16.000s	1.855ms	49	50	98.00
		aes_control_fi	47.000s	10.145ms	278	300	92.67
		aes_cipher_fi	49.000s	10.003ms	334	350	95.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	6.000s	119.580us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	6.000s	119.580us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	6.000s	119.580us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	6.000s	119.580us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	7.000s	1.930ms	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	11.000s	1.893ms	5	5	100.00
		aes_tl_intg_err	7.000s	291.128us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	7.000s	291.128us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	17.000s	863.371us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	6.000s	119.580us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	10.000s	490.698us	50	50	100.00
		aes_stress	16.000s	665.628us	50	50	100.00
		aes_alert_reset	17.000s	863.371us	50	50	100.00
		aes_core_fi	7.000s	205.325us	70	70	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	6.000s	119.580us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	6.000s	216.850us	50	50	100.00
		aes_stress	16.000s	665.628us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	16.000s	665.628us	50	50	100.00
		aes_sideload	16.000s	659.653us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	216.850us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	216.850us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	216.850us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	216.850us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	216.850us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	16.000s	665.628us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	16.000s	665.628us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	16.000s	1.855ms	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	16.000s	1.855ms	49	50	98.00
		aes_control_fi	47.000s	10.145ms	278	300	92.67
		aes_cipher_fi	49.000s	10.003ms	334	350	95.43
		aes_ctr_fi	16.000s	1.822ms	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	16.000s	1.855ms	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	16.000s	1.855ms	49	50	98.00
		aes_control_fi	47.000s	10.145ms	278	300	92.67
		aes_cipher_fi	49.000s	10.003ms	334	350	95.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	10.003ms	334	350	95.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	16.000s	1.855ms	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	16.000s	1.855ms	49	50	98.00
		aes_control_fi	47.000s	10.145ms	278	300	92.67
		aes_ctr_fi	16.000s	1.822ms	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	16.000s	1.855ms	49	50	98.00
		aes_control_fi	47.000s	10.145ms	278	300	92.67
		aes_cipher_fi	49.000s	10.003ms	334	350	95.43
		aes_ctr_fi	16.000s	1.822ms	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	17.000s	863.371us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	16.000s	1.855ms	49	50	98.00
		aes_control_fi	47.000s	10.145ms	278	300	92.67
		aes_cipher_fi	49.000s	10.003ms	334	350	95.43
		aes_ctr_fi	16.000s	1.822ms	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	16.000s	1.855ms	49	50	98.00
		aes_control_fi	47.000s	10.145ms	278	300	92.67
		aes_cipher_fi	49.000s	10.003ms	334	350	95.43
		aes_ctr_fi	16.000s	1.822ms	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	16.000s	1.855ms	49	50	98.00
		aes_control_fi	47.000s	10.145ms	278	300	92.67
		aes_ctr_fi	16.000s	1.822ms	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	16.000s	1.855ms	49	50	98.00
		aes_control_fi	47.000s	10.145ms	278	300	92.67
		aes_cipher_fi	49.000s	10.003ms	334	350	95.43
V2S		TOTAL			946	985	96.04
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	26.000s	689.738us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1553	1602	96.94

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.41	98.64	96.54	99.45	95.58	97.99	97.78	98.96	98.39

Failure Buckets

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 16 failures:
- Test aes_cipher_fi has 16 failures.
  - 2.aes_cipher_fi.95886151761615508539977084871662021322381406751919930198407902225398913616819
    Line 145, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/2.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10014229409 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014229409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 7.aes_cipher_fi.18425817716277591355195403420907141731941652777641074590702262316301622563311
    Line 147, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/7.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10036698417 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10036698417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 14 more failures.
Job timed out after * minutes has 12 failures:
- Test aes_control_fi has 12 failures.
  - 35.aes_control_fi.62252118634278609426530515352123791691670619914976985609061264306862363864084
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/35.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 48.aes_control_fi.28308951785887483789598994447298973166359365356949152620575650838438597378974
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/48.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 10 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 40.aes_control_fi.20560607025797196092469915803730573498667491234917712707410907133081955946382
    Line 138, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/40.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10028441212 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10028441212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 89.aes_control_fi.92138393538044581699088683539656889951353724056048982610851858738124476903136
    Line 139, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/89.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10045846543 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10045846543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

3.aes_stress_all_with_rand_reset.23873118476186072898988184403076097307829872692661081801160444004029184861969
Line 641, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 392542966 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 392542966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.69106117685181070068011412787115916064959394806093371482008461963963539546584
Line 840, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 443073066 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 443073066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 0.aes_stress_all_with_rand_reset.58309015578443983475952703100404337180683574020933469386467722972279507879714
    Line 202, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 101405069 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 101405069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.aes_stress_all_with_rand_reset.5934184493315005602646935232461733927202007549696384236473659355008744974817
    Line 394, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 207669708 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 207669708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 2.aes_stress_all_with_rand_reset.13064403197296717466916979626899729280210299510446676823893514267611574901738
    Line 415, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2006777034 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 2006777034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.aes_stress_all_with_rand_reset.20831528540514281958559106306294273776777805378934666165910540931984472595079
    Line 178, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 497520216 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 497520216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:929) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 5.aes_stress_all_with_rand_reset.115449499455701819892785724354176227908371310244159973960924831200419093718766
    Line 179, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 710578063 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 710578063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 7.aes_stress_all_with_rand_reset.49438267409772832684434673669696047052744412044527202932569183101775800608015
    Line 265, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 689738307 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 689738307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_fi has 1 failures.

14.aes_fi.65727277028566977093636527194177460090486198692038919690232533520653424567733
Line 1410, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/14.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 9304796 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 9282574 PS)
  UVM_ERROR @   9304796 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @   9304796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_control_fi has 1 failures.
  - 223.aes_control_fi.79757473748751905880896419021961484634636682771362173924245034717489760650446
    Line 133, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/223.aes_control_fi/latest/run.log
```
  UVM_ERROR @  25024933 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  25024933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```