AES/UNMASKED Simulation Results

Sunday June 01 2025 00:07:48 UTC

GitHub Revision: `a4c7f98`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	66.424us	1	1	100.00
V1	smoke	aes_smoke	6.000s	145.891us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	36.000s	51.685us	5	5	100.00
V1	csr_rw	aes_csr_rw	36.000s	63.735us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	41.000s	326.607us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	37.000s	1.122ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	37.000s	170.987us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	36.000s	63.735us	20	20	100.00
		aes_csr_aliasing	37.000s	1.122ms	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	6.000s	145.891us	50	50	100.00
		aes_config_error	6.000s	102.361us	50	50	100.00
		aes_stress	7.000s	176.427us	50	50	100.00
V2	key_length	aes_smoke	6.000s	145.891us	50	50	100.00
		aes_config_error	6.000s	102.361us	50	50	100.00
		aes_stress	7.000s	176.427us	50	50	100.00
V2	back2back	aes_stress	7.000s	176.427us	50	50	100.00
		aes_b2b	11.000s	570.043us	50	50	100.00
V2	backpressure	aes_stress	7.000s	176.427us	50	50	100.00
V2	multi_message	aes_smoke	6.000s	145.891us	50	50	100.00
		aes_config_error	6.000s	102.361us	50	50	100.00
		aes_stress	7.000s	176.427us	50	50	100.00
		aes_alert_reset	6.000s	105.410us	50	50	100.00
V2	failure_test	aes_man_cfg_err	6.000s	59.869us	50	50	100.00
		aes_config_error	6.000s	102.361us	50	50	100.00
		aes_alert_reset	6.000s	105.410us	50	50	100.00
V2	trigger_clear_test	aes_clear	7.000s	230.621us	49	50	98.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	162.973us	1	1	100.00
V2	reset_recovery	aes_alert_reset	6.000s	105.410us	50	50	100.00
V2	stress	aes_stress	7.000s	176.427us	50	50	100.00
V2	sideload	aes_stress	7.000s	176.427us	50	50	100.00
		aes_sideload	6.000s	134.229us	50	50	100.00
V2	deinitialization	aes_deinit	7.000s	628.712us	50	50	100.00
V2	stress_all	aes_stress_all	19.000s	1.534ms	10	10	100.00
V2	alert_test	aes_alert_test	6.000s	74.133us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	37.000s	159.692us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	37.000s	159.692us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	36.000s	51.685us	5	5	100.00
		aes_csr_rw	36.000s	63.735us	20	20	100.00
		aes_csr_aliasing	37.000s	1.122ms	5	5	100.00
		aes_same_csr_outstanding	36.000s	56.840us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	36.000s	51.685us	5	5	100.00
		aes_csr_rw	36.000s	63.735us	20	20	100.00
		aes_csr_aliasing	37.000s	1.122ms	5	5	100.00
		aes_same_csr_outstanding	36.000s	56.840us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	16.000s	798.080us	50	50	100.00
V2S	fault_inject	aes_fi	6.000s	208.235us	48	50	96.00
		aes_control_fi	45.000s	10.003ms	287	300	95.67
		aes_cipher_fi	30.000s	10.007ms	329	350	94.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	36.000s	62.906us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	36.000s	62.906us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	36.000s	62.906us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	36.000s	62.906us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	36.000s	431.497us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	831.182us	5	5	100.00
		aes_tl_intg_err	37.000s	268.103us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	37.000s	268.103us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	6.000s	105.410us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	36.000s	62.906us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	6.000s	145.891us	50	50	100.00
		aes_stress	7.000s	176.427us	50	50	100.00
		aes_alert_reset	6.000s	105.410us	50	50	100.00
		aes_core_fi	4.550m	10.008ms	62	70	88.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	36.000s	62.906us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	6.000s	116.538us	50	50	100.00
		aes_stress	7.000s	176.427us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	7.000s	176.427us	50	50	100.00
		aes_sideload	6.000s	134.229us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	116.538us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	116.538us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	116.538us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	116.538us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	116.538us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	7.000s	176.427us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	7.000s	176.427us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	6.000s	208.235us	48	50	96.00
V2S	sec_cm_main_fsm_redun	aes_fi	6.000s	208.235us	48	50	96.00
		aes_control_fi	45.000s	10.003ms	287	300	95.67
		aes_cipher_fi	30.000s	10.007ms	329	350	94.00
		aes_ctr_fi	6.000s	61.413us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	6.000s	208.235us	48	50	96.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	6.000s	208.235us	48	50	96.00
		aes_control_fi	45.000s	10.003ms	287	300	95.67
		aes_cipher_fi	30.000s	10.007ms	329	350	94.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	30.000s	10.007ms	329	350	94.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	6.000s	208.235us	48	50	96.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	6.000s	208.235us	48	50	96.00
		aes_control_fi	45.000s	10.003ms	287	300	95.67
		aes_ctr_fi	6.000s	61.413us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	6.000s	208.235us	48	50	96.00
		aes_control_fi	45.000s	10.003ms	287	300	95.67
		aes_cipher_fi	30.000s	10.007ms	329	350	94.00
		aes_ctr_fi	6.000s	61.413us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	6.000s	105.410us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	6.000s	208.235us	48	50	96.00
		aes_control_fi	45.000s	10.003ms	287	300	95.67
		aes_cipher_fi	30.000s	10.007ms	329	350	94.00
		aes_ctr_fi	6.000s	61.413us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	6.000s	208.235us	48	50	96.00
		aes_control_fi	45.000s	10.003ms	287	300	95.67
		aes_cipher_fi	30.000s	10.007ms	329	350	94.00
		aes_ctr_fi	6.000s	61.413us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	6.000s	208.235us	48	50	96.00
		aes_control_fi	45.000s	10.003ms	287	300	95.67
		aes_ctr_fi	6.000s	61.413us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	6.000s	208.235us	48	50	96.00
		aes_control_fi	45.000s	10.003ms	287	300	95.67
		aes_cipher_fi	30.000s	10.007ms	329	350	94.00
V2S		TOTAL			941	985	95.53
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	24.000s	1.439ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1547	1602	96.57

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.28	97.71	94.84	98.82	93.37	97.99	91.11	98.85	96.98

Failure Buckets

Job timed out after * minutes has 19 failures:
- Test aes_cipher_fi has 11 failures.
  - 14.aes_cipher_fi.26513183654958363338659201202004858684931743667278605365585896725527814636121
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/14.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 32.aes_cipher_fi.40746665998774589106642773049243453162953776978702939595999930677042707560119
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/32.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 9 more failures.
- Test aes_control_fi has 8 failures.
  - 21.aes_control_fi.89134364526898288017574573645101394074228273707750349335931724459933439412292
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/21.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 23.aes_control_fi.43761737551955051095572978230725265998120235361660318724329336309320768029009
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/23.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 6 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_cipher_fi has 10 failures.
  - 44.aes_cipher_fi.70668989319256176842153640652347070649510755151166829618497296541225402427700
    Line 148, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/44.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10004102240 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004102240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 52.aes_cipher_fi.103521215444303884018665610253153388449361882283335517637679225748494322620866
    Line 140, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/52.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006643774 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006643774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 8 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.14176601540932364650075563577910830824998429606280082861789432943279586843882
Line 200, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 697629143 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 697629143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.16045503891108157984910831246548834464976813031485574369572873649089518389014
Line 1219, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 393676924 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 393676924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_control_fi has 5 failures.
  - 11.aes_control_fi.33299764494613872936664962183448660830829078452172181767140237127109643682417
    Line 137, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/11.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10004949213 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004949213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 32.aes_control_fi.77962947968019983361055296667771715998446591693443300478103414454749375204167
    Line 133, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/32.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10008465567 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008465567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_core_fi has 4 failures.
  - 7.aes_core_fi.83243359980108510173484047323752170481628630228682313362466489589115875454628
    Line 145, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/7.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10012528722 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012528722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 38.aes_core_fi.50492356276173726484168251507221329727911424752337148886635858570885097628306
    Line 139, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/38.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10003065062 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003065062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 2.aes_stress_all_with_rand_reset.57941004041239045356714409945685539389808562923418072431085200453344213546187
    Line 965, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 322956566 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 322956566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.aes_stress_all_with_rand_reset.23688272129176633321106271046725668950723992281531114197297410319201402842885
    Line 386, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 3932371498 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 3932371498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 2 failures:

Test aes_core_fi has 2 failures.

28.aes_core_fi.107637034621800181406688289309483314857386710307596867023346692624163160625663
Line 131, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/28.aes_core_fi/latest/run.log

  UVM_FATAL @ 10036733910 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x9d9e484, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10036733910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

61.aes_core_fi.64636148784633849911584770580606017629531349850636350830173197860519885569221
Line 132, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/61.aes_core_fi/latest/run.log

  UVM_FATAL @ 10047609036 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x8d98d584, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10047609036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:929) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.12516894369886653077096081652537413130833952209755682099490668980967290529290
    Line 155, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 762640929 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 762640929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 13.aes_core_fi.97006108865450826978858770757358034009507539401410724257624890716395655333191
    Line 133, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/13.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10016088752 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x5e303a84, Comparison=CompareOpEq, exp_data=0x0, call_count=6)
  UVM_INFO @ 10016088752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 14.aes_core_fi.54458999887226518199576522400469657610584875191804756678649232132440139545561
    Line 132, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/14.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008386849 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xdd54984, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
  UVM_INFO @ 10008386849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_fi has 1 failures.

24.aes_fi.47812379787113957884029570536569393656730871151688552022528545558712199804197
Line 2437, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/24.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 76812132 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 76701021 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 76812132 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 76701021 PS)
  UVM_ERROR @  76812132 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:

Test aes_fi has 1 failures.

30.aes_fi.20632892412639156026052633391344997840288158093312264004446118438814990266797
Line 3120, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/30.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 34515006 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 34473339 PS)
  UVM_ERROR @  34515006 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  34515006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_scoreboard.sv:611) scoreboard [scoreboard] # * has 1 failures:
- Test aes_clear has 1 failures.
  - 43.aes_clear.70199406543303682410622595900555273982680115015219524923271649177440569954820
    Line 1773, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/43.aes_clear/latest/run.log
```
  UVM_FATAL @  47054013 ps: (aes_scoreboard.sv:611) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]  # 0
           TEST FAILED MESSAGES DID NOT MATCH

                 0 47 	 03 	 fe 	 0
                 1 cc 	 26 	 04 	 0
```