AON_TIMER Simulation Results

Sunday June 01 2025 00:07:48 UTC

GitHub Revision: a4c7f98

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	2.670s	485.338us	5	5	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	3.720s	1.242ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	3.380s	419.251us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	14.490s	7.179ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	3.230s	625.567us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	2.900s	437.509us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	3.380s	419.251us	20	20	100.00
		aon_timer_csr_aliasing	3.230s	625.567us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	2.510s	458.977us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	2.460s	372.566us	5	5	100.00
V1		TOTAL			70	70	100.00
V2	prescaler	aon_timer_prescaler	1.397m	59.759ms	15	15	100.00
V2	jump	aon_timer_jump	3.760s	720.621us	5	5	100.00
V2	stress_all	aon_timer_stress_all	2.733m	116.369ms	15	15	100.00
V2	alert_test	aon_timer_alert_test	3.090s	427.499us	50	50	100.00
V2	intr_test	aon_timer_intr_test	3.200s	517.130us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	4.480s	1.122ms	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	4.480s	1.122ms	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	3.720s	1.242ms	5	5	100.00
		aon_timer_csr_rw	3.380s	419.251us	20	20	100.00
		aon_timer_csr_aliasing	3.230s	625.567us	5	5	100.00
		aon_timer_same_csr_outstanding	6.500s	2.041ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	3.720s	1.242ms	5	5	100.00
		aon_timer_csr_rw	3.380s	419.251us	20	20	100.00
		aon_timer_csr_aliasing	3.230s	625.567us	5	5	100.00
		aon_timer_same_csr_outstanding	6.500s	2.041ms	20	20	100.00
V2		TOTAL			175	175	100.00
V2S	tl_intg_err	aon_timer_sec_cm	11.730s	7.664ms	5	5	100.00
		aon_timer_tl_intg_err	16.670s	8.883ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	16.670s	8.883ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	max_threshold	aon_timer_smoke_max_thold	2.290s	701.652us	5	5	100.00
V3	min_threshold	aon_timer_smoke_min_thold	2.730s	642.723us	5	5	100.00
V3	wkup_count_hi_cdc	aon_timer_wkup_count_cdc_hi	12.700s	3.904ms	5	5	100.00
V3	custom_intr	aon_timer_custom_intr	3.650s	691.401us	10	10	100.00
V3	alternating_on_off	aon_timer_alternating_enable_on_off	22.880s	4.132ms	5	5	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	35.590s	15.093ms	15	15	100.00
V3		TOTAL			45	45	100.00
		TOTAL			315	315	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.29	99.09	99.05	100.00	--	98.56	99.05	100.00