CSRNG Simulation Results

Sunday June 01 2025 00:07:48 UTC

GitHub Revision: `a4c7f98`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	9.000s	258.068us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	34.000s	33.843us	5	5	100.00
V1	csr_rw	csrng_csr_rw	31.000s	19.674us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	32.000s	70.414us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	17.000s	114.181us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	9.000s	383.390us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	31.000s	19.674us	20	20	100.00
		csrng_csr_aliasing	17.000s	114.181us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	25.000s	1.176ms	199	200	99.50
V2	alerts	csrng_alert	1.083m	5.579ms	500	500	100.00
V2	err	csrng_err	10.000s	41.477us	500	500	100.00
V2	cmds	csrng_cmds	5.017m	18.273ms	50	50	100.00
V2	life cycle	csrng_cmds	5.017m	18.273ms	50	50	100.00
V2	stress_all	csrng_stress_all	26.317m	144.148ms	48	50	96.00
V2	intr_test	csrng_intr_test	39.000s	31.654us	50	50	100.00
V2	alert_test	csrng_alert_test	8.000s	131.815us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	52.000s	606.610us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	52.000s	606.610us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	34.000s	33.843us	5	5	100.00
		csrng_csr_rw	31.000s	19.674us	20	20	100.00
		csrng_csr_aliasing	17.000s	114.181us	5	5	100.00
		csrng_same_csr_outstanding	9.000s	107.244us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	34.000s	33.843us	5	5	100.00
		csrng_csr_rw	31.000s	19.674us	20	20	100.00
		csrng_csr_aliasing	17.000s	114.181us	5	5	100.00
		csrng_same_csr_outstanding	9.000s	107.244us	20	20	100.00
V2		TOTAL			1437	1440	99.79
V2S	tl_intg_err	csrng_sec_cm	48.000s	1.184ms	5	5	100.00
		csrng_tl_intg_err	45.000s	386.249us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	7.000s	134.613us	50	50	100.00
		csrng_csr_rw	31.000s	19.674us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.083m	5.579ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	26.317m	144.148ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	25.000s	1.176ms	199	200	99.50
		csrng_err	10.000s	41.477us	500	500	100.00
		csrng_sec_cm	48.000s	1.184ms	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	25.000s	1.176ms	199	200	99.50
		csrng_err	10.000s	41.477us	500	500	100.00
		csrng_sec_cm	48.000s	1.184ms	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	25.000s	1.176ms	199	200	99.50
		csrng_err	10.000s	41.477us	500	500	100.00
		csrng_sec_cm	48.000s	1.184ms	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	25.000s	1.176ms	199	200	99.50
		csrng_err	10.000s	41.477us	500	500	100.00
		csrng_sec_cm	48.000s	1.184ms	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	25.000s	1.176ms	199	200	99.50
		csrng_err	10.000s	41.477us	500	500	100.00
		csrng_sec_cm	48.000s	1.184ms	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	25.000s	1.176ms	199	200	99.50
		csrng_err	10.000s	41.477us	500	500	100.00
		csrng_sec_cm	48.000s	1.184ms	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	25.000s	1.176ms	199	200	99.50
		csrng_err	10.000s	41.477us	500	500	100.00
		csrng_sec_cm	48.000s	1.184ms	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.083m	5.579ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	25.000s	1.176ms	199	200	99.50
		csrng_err	10.000s	41.477us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	26.317m	144.148ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.083m	5.579ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	45.000s	386.249us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	25.000s	1.176ms	199	200	99.50
		csrng_err	10.000s	41.477us	500	500	100.00
		csrng_sec_cm	48.000s	1.184ms	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	25.000s	1.176ms	199	200	99.50
		csrng_err	10.000s	41.477us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	25.000s	1.176ms	199	200	99.50
		csrng_err	10.000s	41.477us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	25.000s	1.176ms	199	200	99.50
		csrng_err	10.000s	41.477us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	25.000s	1.176ms	199	200	99.50
		csrng_err	10.000s	41.477us	500	500	100.00
		csrng_sec_cm	48.000s	1.184ms	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	25.000s	1.176ms	199	200	99.50
		csrng_err	10.000s	41.477us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.067m	1.468ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1617	1630	99.20

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.67	98.58	96.56	99.91	97.42	91.96	100.00	97.01	90.15

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:929) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
- Test csrng_stress_all_with_rand_reset has 9 failures.
  - 1.csrng_stress_all_with_rand_reset.41964704444683076211481776002762081266091437450245514510381652994651117034589
    Line 107, in log /nightly/runs/scratch/master/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1468203113 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1468203113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.csrng_stress_all_with_rand_reset.26034446090796582363562631398785374000093957429347163775971172809457163860567
    Line 103, in log /nightly/runs/scratch/master/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1508010341 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1508010341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.

UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:

Test csrng_stress_all has 2 failures.

5.csrng_stress_all.58000736048102544378116616737523105004962962487345466919290726289940094976949
Line 134, in log /nightly/runs/scratch/master/csrng-sim-xcelium/5.csrng_stress_all/latest/run.log

  UVM_ERROR @  63871674 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  63871674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

30.csrng_stress_all.66146629448609900836146212347353115233229355103696089578182324749478709220952
Line 182, in log /nightly/runs/scratch/master/csrng-sim-xcelium/30.csrng_stress_all/latest/run.log

  UVM_ERROR @ 32555751051 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 32555751051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started has 1 failures:
- Test csrng_stress_all_with_rand_reset has 1 failures.
  - 0.csrng_stress_all_with_rand_reset.105696956151014707119713301491046329018360362047345177043237219216724536314011
    Line 107, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  43467678 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
  UVM_INFO @  43467678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,518): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 1 failures:

Test csrng_intr has 1 failures.

159.csrng_intr.67855571255732120981697054282038341203283281905177874593161544906760545980572
Line 133, in log /nightly/runs/scratch/master/csrng-sim-xcelium/159.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 143019556 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @ 143019556 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @ 143019556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---