EDN Simulation Results

Sunday June 01 2025 00:07:48 UTC

GitHub Revision: a4c7f98

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 2.590s 18.242us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 2.020s 33.084us 5 5 100.00
V1 csr_rw edn_csr_rw 2.270s 40.853us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 6.490s 252.034us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 3.010s 40.774us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.910s 138.317us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 2.270s 40.853us 20 20 100.00
edn_csr_aliasing 3.010s 40.774us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 5.420s 817.698us 300 300 100.00
V2 csrng_commands edn_genbits 5.420s 817.698us 300 300 100.00
V2 genbits edn_genbits 5.420s 817.698us 300 300 100.00
V2 interrupts edn_intr 2.780s 24.894us 50 50 100.00
V2 alerts edn_alert 2.940s 334.907us 200 200 100.00
V2 errs edn_err 2.780s 18.886us 100 100 100.00
V2 disable edn_disable 2.510s 35.113us 50 50 100.00
edn_disable_auto_req_mode 2.950s 57.413us 50 50 100.00
V2 stress_all edn_stress_all 7.720s 419.731us 50 50 100.00
V2 intr_test edn_intr_test 2.300s 207.163us 50 50 100.00
V2 alert_test edn_alert_test 2.760s 59.194us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 5.550s 1.992ms 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 5.550s 1.992ms 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 2.020s 33.084us 5 5 100.00
edn_csr_rw 2.270s 40.853us 20 20 100.00
edn_csr_aliasing 3.010s 40.774us 5 5 100.00
edn_same_csr_outstanding 2.510s 39.651us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 2.020s 33.084us 5 5 100.00
edn_csr_rw 2.270s 40.853us 20 20 100.00
edn_csr_aliasing 3.010s 40.774us 5 5 100.00
edn_same_csr_outstanding 2.510s 39.651us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 8.320s 602.714us 5 5 100.00
edn_tl_intg_err 3.800s 166.160us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 2.170s 27.191us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 2.940s 334.907us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 8.320s 602.714us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 8.320s 602.714us 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 8.320s 602.714us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 8.320s 602.714us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 2.940s 334.907us 200 200 100.00
edn_sec_cm 8.320s 602.714us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 2.940s 334.907us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 3.800s 166.160us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 2.132m 65.144ms 31 50 62.00
V3 TOTAL 31 50 62.00
TOTAL 1111 1130 98.32

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.92 98.87 94.23 97.02 91.86 96.33 99.78 93.32

Failure Buckets