ENTROPY_SRC Simulation Results

Sunday June 01 2025 00:07:48 UTC

GitHub Revision: a4c7f98

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 9.000s 65.842us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 5.000s 116.368us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 5.000s 23.639us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 15.000s 9.543ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 9.000s 209.200us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 6.000s 45.379us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 5.000s 23.639us 20 20 100.00
entropy_src_csr_aliasing 9.000s 209.200us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 9.000s 65.842us 50 50 100.00
entropy_src_rng 5.350m 13.030ms 13 300 4.33
entropy_src_fw_ov 8.783m 20.043ms 185 300 61.67
V2 firmware_mode entropy_src_fw_ov 8.783m 20.043ms 185 300 61.67
V2 rng_mode entropy_src_rng 5.350m 13.030ms 13 300 4.33
V2 rng_max_rate entropy_src_rng_max_rate 6.683m 11.236ms 5 400 1.25
V2 health_checks entropy_src_rng 5.350m 13.030ms 13 300 4.33
V2 conditioning entropy_src_rng 5.350m 13.030ms 13 300 4.33
V2 interrupts entropy_src_rng 5.350m 13.030ms 13 300 4.33
entropy_src_intr 34.000s 1.001ms 50 50 100.00
V2 alerts entropy_src_rng 5.350m 13.030ms 13 300 4.33
entropy_src_functional_alerts 9.000s 57.049us 50 50 100.00
V2 stress_all entropy_src_stress_all 6.500m 19.046ms 49 50 98.00
V2 functional_errors entropy_src_functional_errors 6.650m 10.013ms 958 1000 95.80
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 33.000s 336.393us 50 50 100.00
V2 intr_test entropy_src_intr_test 5.000s 22.312us 50 50 100.00
V2 alert_test entropy_src_alert_test 9.000s 139.867us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 8.000s 115.882us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 8.000s 115.882us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 5.000s 116.368us 5 5 100.00
entropy_src_csr_rw 5.000s 23.639us 20 20 100.00
entropy_src_csr_aliasing 9.000s 209.200us 5 5 100.00
entropy_src_same_csr_outstanding 7.000s 1.168ms 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 5.000s 116.368us 5 5 100.00
entropy_src_csr_rw 5.000s 23.639us 20 20 100.00
entropy_src_csr_aliasing 9.000s 209.200us 5 5 100.00
entropy_src_same_csr_outstanding 7.000s 1.168ms 20 20 100.00
V2 TOTAL 1500 2340 64.10
V2S tl_intg_err entropy_src_sec_cm 9.000s 98.131us 5 5 100.00
entropy_src_tl_intg_err 9.000s 817.304us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 5.350m 13.030ms 13 300 4.33
entropy_src_cfg_regwen 8.000s 45.478us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 5.350m 13.030ms 13 300 4.33
V2S sec_cm_config_redun entropy_src_rng 5.350m 13.030ms 13 300 4.33
V2S sec_cm_intersig_mubi entropy_src_rng 5.350m 13.030ms 13 300 4.33
entropy_src_fw_ov 8.783m 20.043ms 185 300 61.67
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 6.650m 10.013ms 958 1000 95.80
entropy_src_sec_cm 9.000s 98.131us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 6.650m 10.013ms 958 1000 95.80
entropy_src_sec_cm 9.000s 98.131us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 5.350m 13.030ms 13 300 4.33
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 6.650m 10.013ms 958 1000 95.80
entropy_src_sec_cm 9.000s 98.131us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 6.650m 10.013ms 958 1000 95.80
entropy_src_sec_cm 9.000s 98.131us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 6.650m 10.013ms 958 1000 95.80
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 9.000s 57.049us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 9.000s 817.304us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 6.117m 13.529ms 5 50 10.00
V3 TOTAL 5 50 10.00
TOTAL 1685 2570 65.56

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
95.89 98.17 95.37 98.35 95.41 96.38 96.88 91.01 84.87

Failure Buckets