HMAC Simulation Results

Sunday June 01 2025 00:07:48 UTC

GitHub Revision: a4c7f98

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	18.480s	1.497ms	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	2.410s	41.577us	5	5	100.00
V1	csr_rw	hmac_csr_rw	2.450s	268.238us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	16.030s	325.427us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	9.560s	1.010ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	10.121m	304.847ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	2.450s	268.238us	20	20	100.00
		hmac_csr_aliasing	9.560s	1.010ms	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	1.357m	4.758ms	10	10	100.00
V2	back_pressure	hmac_back_pressure	1.550m	2.133ms	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	5.093m	6.556ms	30	30	100.00
		hmac_test_sha384_vectors	9.818m	16.419ms	75	75	100.00
		hmac_test_sha512_vectors	9.107m	56.415ms	75	75	100.00
		hmac_test_hmac256_vectors	17.140s	1.393ms	50	50	100.00
		hmac_test_hmac384_vectors	20.740s	3.349ms	60	60	100.00
		hmac_test_hmac512_vectors	20.910s	1.665ms	75	75	100.00
V2	burst_wr	hmac_burst_wr	36.480s	13.136ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	14.949m	4.909ms	10	10	100.00
V2	error	hmac_error	2.226m	8.444ms	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	2.692m	11.759ms	10	10	100.00
V2	save_and_restore	hmac_smoke	18.480s	1.497ms	10	10	100.00
		hmac_long_msg	1.357m	4.758ms	10	10	100.00
		hmac_back_pressure	1.550m	2.133ms	25	25	100.00
		hmac_datapath_stress	14.949m	4.909ms	10	10	100.00
		hmac_burst_wr	36.480s	13.136ms	50	50	100.00
		hmac_stress_all	38.898m	499.367ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	18.480s	1.497ms	10	10	100.00
		hmac_long_msg	1.357m	4.758ms	10	10	100.00
		hmac_back_pressure	1.550m	2.133ms	25	25	100.00
		hmac_datapath_stress	14.949m	4.909ms	10	10	100.00
		hmac_wipe_secret	2.692m	11.759ms	10	10	100.00
		hmac_test_sha256_vectors	5.093m	6.556ms	30	30	100.00
		hmac_test_sha384_vectors	9.818m	16.419ms	75	75	100.00
		hmac_test_sha512_vectors	9.107m	56.415ms	75	75	100.00
		hmac_test_hmac256_vectors	17.140s	1.393ms	50	50	100.00
		hmac_test_hmac384_vectors	20.740s	3.349ms	60	60	100.00
		hmac_test_hmac512_vectors	20.910s	1.665ms	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	18.480s	1.497ms	10	10	100.00
		hmac_long_msg	1.357m	4.758ms	10	10	100.00
		hmac_back_pressure	1.550m	2.133ms	25	25	100.00
		hmac_datapath_stress	14.949m	4.909ms	10	10	100.00
		hmac_burst_wr	36.480s	13.136ms	50	50	100.00
		hmac_error	2.226m	8.444ms	10	10	100.00
		hmac_wipe_secret	2.692m	11.759ms	10	10	100.00
		hmac_test_sha256_vectors	5.093m	6.556ms	30	30	100.00
		hmac_test_sha384_vectors	9.818m	16.419ms	75	75	100.00
		hmac_test_sha512_vectors	9.107m	56.415ms	75	75	100.00
		hmac_test_hmac256_vectors	17.140s	1.393ms	50	50	100.00
		hmac_test_hmac384_vectors	20.740s	3.349ms	60	60	100.00
		hmac_test_hmac512_vectors	20.910s	1.665ms	75	75	100.00
		hmac_stress_all	38.898m	499.367ms	50	50	100.00
V2	stress_all	hmac_stress_all	38.898m	499.367ms	50	50	100.00
V2	alert_test	hmac_alert_test	2.060s	14.161us	50	50	100.00
V2	intr_test	hmac_intr_test	2.180s	34.852us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	5.860s	3.085ms	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	5.860s	3.085ms	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	2.410s	41.577us	5	5	100.00
		hmac_csr_rw	2.450s	268.238us	20	20	100.00
		hmac_csr_aliasing	9.560s	1.010ms	5	5	100.00
		hmac_same_csr_outstanding	3.610s	134.319us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	2.410s	41.577us	5	5	100.00
		hmac_csr_rw	2.450s	268.238us	20	20	100.00
		hmac_csr_aliasing	9.560s	1.010ms	5	5	100.00
		hmac_same_csr_outstanding	3.610s	134.319us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	3.300s	1.758ms	5	5	100.00
		hmac_tl_intg_err	6.100s	284.735us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	6.100s	284.735us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	18.480s	1.497ms	10	10	100.00
V3	stress_reset	hmac_stress_reset	8.230s	399.787us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	10.372m	23.317ms	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	2.180s	37.964us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.96	99.84	97.25	100.00	100.00	99.83	99.52	47.30