I2C Simulation Results

Sunday June 01 2025 00:07:48 UTC

GitHub Revision: `a4c7f98`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.500m	16.965ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	41.770s	11.751ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	2.120s	26.847us	5	5	100.00
V1	csr_rw	i2c_csr_rw	2.370s	40.820us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	5.100s	1.069ms	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.730s	200.229us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.390s	352.653us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	2.370s	40.820us	20	20	100.00
		i2c_csr_aliasing	2.730s	200.229us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	13.490s	1.572ms	50	50	100.00
V2	host_stress_all	i2c_host_stress_all	33.896m	56.925ms	16	50	32.00
V2	host_maxperf	i2c_host_perf	28.726m	18.893ms	50	50	100.00
V2	host_override	i2c_host_override	2.850s	31.047us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	4.804m	4.945ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.080m	2.529ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.950s	190.199us	50	50	100.00
		i2c_host_fifo_fmt_empty	21.630s	545.281us	50	50	100.00
		i2c_host_fifo_reset_rx	12.720s	403.889us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	2.689m	13.411ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	37.020s	918.763us	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	8.090s	387.212us	18	50	36.00
V2	target_glitch	i2c_target_glitch	9.960s	16.087ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	16.439m	57.829ms	48	50	96.00
V2	target_maxperf	i2c_target_perf	8.450s	3.442ms	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	55.530s	5.951ms	50	50	100.00
		i2c_target_intr_smoke	11.020s	1.738ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	3.730s	324.597us	50	50	100.00
		i2c_target_fifo_reset_tx	3.720s	262.976us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	17.740m	58.812ms	50	50	100.00
		i2c_target_stress_rd	55.530s	5.951ms	50	50	100.00
		i2c_target_intr_stress_wr	5.637m	21.931ms	49	50	98.00
V2	target_timeout	i2c_target_timeout	11.290s	6.147ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	4.125m	4.947ms	47	50	94.00
V2	bad_address	i2c_target_bad_addr	10.140s	3.633ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	29.660s	10.004ms	26	50	52.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	4.880s	592.456us	50	50	100.00
		i2c_target_fifo_watermarks_tx	3.380s	192.248us	49	50	98.00
V2	host_mode_config_perf	i2c_host_perf	28.726m	18.893ms	50	50	100.00
		i2c_host_perf_precise	5.477m	23.186ms	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	37.020s	918.763us	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	12.530s	827.953us	49	50	98.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	5.420s	2.249ms	50	50	100.00
		i2c_target_nack_acqfull_addr	5.040s	564.272us	50	50	100.00
		i2c_target_nack_txstretch	3.420s	206.123us	31	50	62.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	23.250s	7.082ms	50	50	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	4.640s	537.919us	50	50	100.00
V2	alert_test	i2c_alert_test	2.250s	19.000us	50	50	100.00
V2	intr_test	i2c_intr_test	2.260s	79.495us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	4.370s	129.784us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	4.370s	129.784us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	2.120s	26.847us	5	5	100.00
		i2c_csr_rw	2.370s	40.820us	20	20	100.00
		i2c_csr_aliasing	2.730s	200.229us	5	5	100.00
		i2c_same_csr_outstanding	2.750s	214.941us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	2.120s	26.847us	5	5	100.00
		i2c_csr_rw	2.370s	40.820us	20	20	100.00
		i2c_csr_aliasing	2.730s	200.229us	5	5	100.00
		i2c_same_csr_outstanding	2.750s	214.941us	20	20	100.00
V2		TOTAL			1675	1792	93.47
V2S	tl_intg_err	i2c_tl_intg_err	3.350s	157.359us	20	20	100.00
		i2c_sec_cm	2.290s	41.054us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	3.350s	157.359us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	25.710s	8.753ms	0	10	0.00
V3	target_error_intr	i2c_target_unexp_stop	3.510s	1.197ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	6.541m	600.000ms	0	10	0.00
V3		TOTAL			0	70	0.00
		TOTAL			1855	2042	90.84

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.00	97.50	89.85	74.17	72.02	94.18	98.52	89.75

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 35 failures:

Test i2c_host_stress_all has 20 failures.

1.i2c_host_stress_all.94805577757661783578097292986460882172301878290528051710566642801022067666690
Line 216, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 105956078882 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @10348248

5.i2c_host_stress_all.31244056900565368869559835056275248432284510646723881786594910122416126373985
Line 295, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 25278174062 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @5505472

... and 18 more failures.

Test i2c_host_mode_toggle has 15 failures.

6.i2c_host_mode_toggle.110878833678890331543973210932952348055838509921678705424137826090806923374667
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/6.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 220222833 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @18453

7.i2c_host_mode_toggle.37829036947677529734374381665350857834815815725514701451728094724570867533320
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 823538651 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @37637

... and 13 more failures.

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 31 failures:
- Test i2c_target_unexp_stop has 31 failures.
  - 0.i2c_target_unexp_stop.78136958045057407605227157004928586166689925693966819431060308070120989415059
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 424298241 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 15 [0xf])
  UVM_INFO @ 424298241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.i2c_target_unexp_stop.78970294050059301441474522619915204900801554170848735891209624520061761800491
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 1196597716 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 105 [0x69])
  UVM_INFO @ 1196597716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 29 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 24 failures:
- Test i2c_target_hrst has 24 failures.
  - 0.i2c_target_hrst.37944608978219327973116685489087652980381756987751113081500022719492876987605
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10943381984 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10943381984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.i2c_target_hrst.110435317632174291199867397159179183797226423995583262234106582709164244692014
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10017869024 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10017869024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 22 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 19 failures:
- Test i2c_target_nack_txstretch has 19 failures.
  - 9.i2c_target_nack_txstretch.7169859475183563967587430100319159669198068958788671022386671612138802194821
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/9.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 578786629 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 578786629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 10.i2c_target_nack_txstretch.67473781495186593526742989235097362944313240731716372047673930031967355277845
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/10.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 688912913 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 688912913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 17 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 17 failures:
- Test i2c_target_unexp_stop has 17 failures.
  - 1.i2c_target_unexp_stop.65149014081245097959303237903650827120296551659809317159006541251209992964223
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 287949122 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 287949122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.i2c_target_unexp_stop.30302399787341163015061289108132104425822463748508555391491568628153771774060
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 1079789992 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1079789992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 15 more failures.

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:

Test i2c_host_stress_all_with_rand_reset has 10 failures.

0.i2c_host_stress_all_with_rand_reset.30169201966927090531283082986565487563887784209229466575939529419959587945366
Line 79, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 382843770 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 382843770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.51334833589075302853027195732080905518504619893154491806419979481366251338639
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 761704295 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 761704295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test i2c_target_stress_all_with_rand_reset has 6 failures.

0.i2c_target_stress_all_with_rand_reset.73191058203789338742380854185719007953345527021950043442824204629984922449073
Line 81, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 747193620 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 747193620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_target_stress_all_with_rand_reset.110718441406405148560416958121237393466460917096749623712373206014175996190452
Line 79, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 212636047 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 212636047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 14 failures:

Test i2c_host_mode_toggle has 14 failures.

0.i2c_host_mode_toggle.113716258531945235318679900026379657483639064692275848408228506959359053230120
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 135072247 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

2.i2c_host_mode_toggle.61245459003153612399677297110837493571176988938987619090473484373565974415423
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 751525543 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

... and 12 more failures.

Job timed out after * minutes has 5 failures:
- Test i2c_host_stress_all has 5 failures.
  - 0.i2c_host_stress_all.77518144394418030646677931067556333221070356618480443513985698115764879232737
    Log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
  - 15.i2c_host_stress_all.111561194547669061342292945635801712401226576120955343125361067138541663837751
    Log /nightly/runs/scratch/master/i2c-sim-vcs/15.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 3 more failures.

UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 5 failures:

Test i2c_host_stress_all has 5 failures.

20.i2c_host_stress_all.775584448399899224658221852581045480018658142683724610023647459334432051035
Line 180, in log /nightly/runs/scratch/master/i2c-sim-vcs/20.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 31787398415 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @403888

25.i2c_host_stress_all.19097656184017731024086511508952981060112388559940424539691216418422382604387
Line 228, in log /nightly/runs/scratch/master/i2c-sim-vcs/25.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 8123024742 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @7328098

... and 3 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 6.i2c_target_stress_all_with_rand_reset.53640867874397216009000809560164423807519873215189149266486222273564670766097
    Line 147, in log /nightly/runs/scratch/master/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_host_stress_all has 3 failures.
  - 12.i2c_host_stress_all.16415825996847828803587484437676709623752919367840860251127212237647033946894
    Line 95, in log /nightly/runs/scratch/master/i2c-sim-vcs/12.i2c_host_stress_all/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 29.i2c_host_stress_all.11581846101062525144494104700462977960853620640220148466841346244212323921626
    Line 89, in log /nightly/runs/scratch/master/i2c-sim-vcs/29.i2c_host_stress_all/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:832) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 3 failures:
- Test i2c_target_stress_all_with_rand_reset has 3 failures.
  - 1.i2c_target_stress_all_with_rand_reset.115090390488411958146161018249253698364813788130378521900283023499290645444457
    Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2710162720 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 2710162720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.i2c_target_stress_all_with_rand_reset.90285677648475327454855241180882860370171170572579653596494026996543615818431
    Line 122, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 381407060 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 381407060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 3 failures:
- Test i2c_target_stress_all has 2 failures.
  - 6.i2c_target_stress_all.107049576680819792460574056124996721656973170467634774233882066005446736200524
    Line 84, in log /nightly/runs/scratch/master/i2c-sim-vcs/6.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 57828859998 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 57828859998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 33.i2c_target_stress_all.101853112470810993759402128241110138330051153637438187329395295116440039014786
    Line 92, in log /nightly/runs/scratch/master/i2c-sim-vcs/33.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 69422869279 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 69422869279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_intr_stress_wr has 1 failures.
  - 29.i2c_target_intr_stress_wr.27582143217182875263009902153509305171924067194097004440620109760985727243425
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/29.i2c_target_intr_stress_wr/latest/run.log
```
  UVM_FATAL @ 38821699230 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 38821699230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 3 failures:
- Test i2c_host_mode_toggle has 3 failures.
  - 9.i2c_host_mode_toggle.97392271066434819512836521127386990626272517956777954375159515606221360575677
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/9.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @ 320673921 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x55ab314, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 320673921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 18.i2c_host_mode_toggle.41698790939896159705889806503371364215682556572931396693522549707041888290495
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/18.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @ 110390265 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x966c0094, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 110390265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 3 failures:
- Test i2c_target_stretch has 3 failures.
  - 11.i2c_target_stretch.17070501118842107248085303409337932464787213181604514518145267708062275588210
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/11.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10046945690 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10046945690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 29.i2c_target_stretch.102933786359501379803584234111804388948974292370120164799537305612259689221479
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/29.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10024736267 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10024736267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 2 failures:

Test i2c_target_unexp_stop has 2 failures.

27.i2c_target_unexp_stop.92383782861772491572420743181073852729712257994486233652399972489707723359150
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/27.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 289711309 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 289711309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.i2c_target_unexp_stop.49718055948082038365992530034812629445838377164719960470446267620897144210877
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/28.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 153164010 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 153164010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Error-[CNST-CIF] Constraints inconsistency failure has 2 failures:
- Test i2c_target_tx_stretch_ctrl has 1 failures.
  - 37.i2c_target_tx_stretch_ctrl.38380216139217448217629377858194484598103000367722369599983292226869481524668
    Line 124, in log /nightly/runs/scratch/master/i2c-sim-vcs/37.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
- Test i2c_target_fifo_watermarks_tx has 1 failures.
  - 41.i2c_target_fifo_watermarks_tx.60314277355627918984108712767184892107618197604744163458233298332585045051664
    Line 115, in log /nightly/runs/scratch/master/i2c-sim-vcs/41.i2c_target_fifo_watermarks_tx/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 1 failures:
- Test i2c_host_stress_all has 1 failures.
  - 14.i2c_host_stress_all.6696565589897573176471769558751780738401335773022338617165985949038446180420
    Line 102, in log /nightly/runs/scratch/master/i2c-sim-vcs/14.i2c_host_stress_all/latest/run.log
```
  UVM_ERROR @ 555863961 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
```