KEYMGR Simulation Results

Sunday June 01 2025 00:07:48 UTC

GitHub Revision: `a4c7f98`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	33.730s	2.725ms	50	50	100.00
V1	random	keymgr_random	1.034m	9.217ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.420s	322.933us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	2.510s	144.209us	18	20	90.00
V1	csr_bit_bash	keymgr_csr_bit_bash	12.180s	5.405ms	2	5	40.00
V1	csr_aliasing	keymgr_csr_aliasing	11.920s	382.943us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	3.130s	303.790us	17	20	85.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.510s	144.209us	18	20	90.00
		keymgr_csr_aliasing	11.920s	382.943us	5	5	100.00
V1		TOTAL			147	155	94.84
V2	cfgen_during_op	keymgr_cfg_regwen	1.232m	21.567ms	50	50	100.00
V2	sideload	keymgr_sideload	38.420s	4.704ms	50	50	100.00
		keymgr_sideload_kmac	42.570s	4.910ms	50	50	100.00
		keymgr_sideload_aes	53.810s	6.288ms	50	50	100.00
		keymgr_sideload_otbn	54.900s	1.816ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	29.030s	4.104ms	49	50	98.00
V2	lc_disable	keymgr_lc_disable	16.390s	1.380ms	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	11.260s	2.780ms	49	50	98.00
V2	invalid_sw_input	keymgr_sw_invalid_input	34.660s	2.498ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	39.620s	7.827ms	49	50	98.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	15.830s	4.175ms	50	50	100.00
V2	stress_all	keymgr_stress_all	2.644m	16.182ms	48	50	96.00
V2	intr_test	keymgr_intr_test	2.370s	44.838us	50	50	100.00
V2	alert_test	keymgr_alert_test	2.570s	40.870us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.220s	1.696ms	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.220s	1.696ms	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.420s	322.933us	5	5	100.00
		keymgr_csr_rw	2.510s	144.209us	18	20	90.00
		keymgr_csr_aliasing	11.920s	382.943us	5	5	100.00
		keymgr_same_csr_outstanding	4.200s	128.219us	16	20	80.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.420s	322.933us	5	5	100.00
		keymgr_csr_rw	2.510s	144.209us	18	20	90.00
		keymgr_csr_aliasing	11.920s	382.943us	5	5	100.00
		keymgr_same_csr_outstanding	4.200s	128.219us	16	20	80.00
V2		TOTAL			731	740	98.78
V2S	sec_cm_additional_check	keymgr_sec_cm	12.800s	1.199ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	12.800s	1.199ms	5	5	100.00
		keymgr_tl_intg_err	6.070s	331.231us	12	20	60.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	6.660s	817.034us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	6.660s	817.034us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	6.660s	817.034us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	6.660s	817.034us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	9.550s	198.272us	14	20	70.00
V2S	prim_count_check	keymgr_sec_cm	12.800s	1.199ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	12.800s	1.199ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	6.070s	331.231us	12	20	60.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	6.660s	817.034us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.232m	21.567ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.034m	9.217ms	50	50	100.00
		keymgr_csr_rw	2.510s	144.209us	18	20	90.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.034m	9.217ms	50	50	100.00
		keymgr_csr_rw	2.510s	144.209us	18	20	90.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.034m	9.217ms	50	50	100.00
		keymgr_csr_rw	2.510s	144.209us	18	20	90.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	16.390s	1.380ms	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	39.620s	7.827ms	49	50	98.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	39.620s	7.827ms	49	50	98.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.034m	9.217ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	21.340s	2.908ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	12.800s	1.199ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	12.800s	1.199ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	12.800s	1.199ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	16.020s	747.407us	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	16.390s	1.380ms	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	12.800s	1.199ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	12.800s	1.199ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	12.800s	1.199ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	16.020s	747.407us	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	16.020s	747.407us	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	12.800s	1.199ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	16.020s	747.407us	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	12.800s	1.199ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	16.020s	747.407us	50	50	100.00
V2S		TOTAL			151	165	91.52
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	26.550s	1.458ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			1053	1110	94.86

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.83	99.13	98.11	98.75	100.00	99.01	98.63	91.16

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 26 failures:

Test keymgr_same_csr_outstanding has 4 failures.

0.keymgr_same_csr_outstanding.104911924790020116839978326250558829051513873395654289132116188959576577720216
Line 80, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[13] & 'hffffffff)))'
  UVM_ERROR @  95797123 ps: (keymgr_csr_assert_fpv.sv:434) [ASSERT FAILED] attest_sw_binding_0_rd_A
  UVM_INFO @  95797123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.keymgr_same_csr_outstanding.115160089659354665370865811230714839699831860444901844285447910125616023465582
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[9] & 'hffffffff)))'
  UVM_ERROR @  35567028 ps: (keymgr_csr_assert_fpv.sv:414) [ASSERT FAILED] sealing_sw_binding_4_rd_A
  UVM_INFO @  35567028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test keymgr_tl_intg_err has 8 failures.

1.keymgr_tl_intg_err.106025948788887658334422790010784324663283053757397018867570163224083728946599
Line 83, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[11] & 'hffffffff)))'
  UVM_ERROR @   8057674 ps: (keymgr_csr_assert_fpv.sv:424) [ASSERT FAILED] sealing_sw_binding_6_rd_A
  UVM_INFO @   8057674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.keymgr_tl_intg_err.23565425016477934010614447023411990999820031365093208737358645932447917829946
Line 79, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[10] & 'hffffffff)))'
  UVM_ERROR @   7015238 ps: (keymgr_csr_assert_fpv.sv:419) [ASSERT FAILED] sealing_sw_binding_5_rd_A
  UVM_INFO @   7015238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test keymgr_csr_rw has 2 failures.

2.keymgr_csr_rw.2718369039681381949633198474928101744798687770048467740858704166349420034328
Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[9] & 'hffffffff)))'
  UVM_ERROR @  19437128 ps: (keymgr_csr_assert_fpv.sv:414) [ASSERT FAILED] sealing_sw_binding_4_rd_A
  UVM_INFO @  19437128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.keymgr_csr_rw.78941083223869661875175349649162677477182635937660559812929831173414931961339
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/9.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[11] & 'hffffffff)))'
  UVM_ERROR @   2553956 ps: (keymgr_csr_assert_fpv.sv:424) [ASSERT FAILED] sealing_sw_binding_6_rd_A
  UVM_INFO @   2553956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_csr_bit_bash has 3 failures.

2.keymgr_csr_bit_bash.45853726587026154230662426329551975107952461558614215481356073418976701509228
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[9] & 'hffffffff)))'
  UVM_ERROR @ 1765086105 ps: (keymgr_csr_assert_fpv.sv:414) [ASSERT FAILED] sealing_sw_binding_4_rd_A
  UVM_INFO @ 1765086105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.keymgr_csr_bit_bash.58223830389474977908169241061763208970445641944847977378220771224769481838631
Line 75, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[20] & 'hffffffff)))'
  UVM_ERROR @ 1216996296 ps: (keymgr_csr_assert_fpv.sv:469) [ASSERT FAILED] attest_sw_binding_7_rd_A
  UVM_INFO @ 1216996296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test keymgr_shadow_reg_errors_with_csr_rw has 6 failures.

5.keymgr_shadow_reg_errors_with_csr_rw.91895073289031787547699023047619395554058902759874771522822758146936770904495
Line 82, in log /nightly/runs/scratch/master/keymgr-sim-vcs/5.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[7] & 'hffffffff)))'
  UVM_ERROR @  38369766 ps: (keymgr_csr_assert_fpv.sv:404) [ASSERT FAILED] sealing_sw_binding_2_rd_A
  UVM_INFO @  38369766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.keymgr_shadow_reg_errors_with_csr_rw.50135951147621170427301605837273896502925434339372421129620639535068389147585
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/7.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[5] & 'hffffffff)))'
  UVM_ERROR @   9385794 ps: (keymgr_csr_assert_fpv.sv:394) [ASSERT FAILED] sealing_sw_binding_0_rd_A
  UVM_INFO @   9385794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

... and 1 more tests.

UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:
- Test keymgr_stress_all_with_rand_reset has 26 failures.
  - 1.keymgr_stress_all_with_rand_reset.107842654600911358386232732844093083629032550608369608937076769487390768907739
    Line 142, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 497767449 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 497767449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.keymgr_stress_all_with_rand_reset.104153705012638893367289467981767948362568166364991257329378260682719852763933
    Line 102, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 404645054 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 404645054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 24 more failures.
UVM_ERROR (cip_base_scoreboard.sv:349) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 2 failures:
- Test keymgr_direct_to_disabled has 1 failures.
  - 10.keymgr_direct_to_disabled.47697705541236154400797784531198679409560477161200043373858541397455436849993
    Line 119, in log /nightly/runs/scratch/master/keymgr-sim-vcs/10.keymgr_direct_to_disabled/latest/run.log
```
  UVM_ERROR @   6871482 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @   6871482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_kmac_rsp_err has 1 failures.
  - 28.keymgr_kmac_rsp_err.76455410941673574016532917055973822774469579230756011935893802123957177565442
    Line 153, in log /nightly/runs/scratch/master/keymgr-sim-vcs/28.keymgr_kmac_rsp_err/latest/run.log
```
  UVM_ERROR @  27190980 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  27190980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 12.keymgr_stress_all.11605486508501892904222570587038304085474020882145468444373771535533887496367
    Line 1504, in log /nightly/runs/scratch/master/keymgr-sim-vcs/12.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 183150724 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (2 [0x2] vs 3 [0x3])
  UVM_INFO @ 183150724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 15.keymgr_stress_all.45108068562780933932002391196825493079659532687417158557353363123183312539658
    Line 220, in log /nightly/runs/scratch/master/keymgr-sim-vcs/15.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @  58826879 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (2306883476 [0x89803f94] vs 2306883476 [0x89803f94]) reg name: keymgr_reg_block.sw_share1_output_7
  UVM_INFO @  58826879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:263) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:
- Test keymgr_hwsw_invalid_input has 1 failures.
  - 27.keymgr_hwsw_invalid_input.12776831260451787782987289653795039103302921540209144477690026231626841468344
    Line 125, in log /nightly/runs/scratch/master/keymgr-sim-vcs/27.keymgr_hwsw_invalid_input/latest/run.log
```
  UVM_ERROR @   9874685 ps: (cip_base_scoreboard.sv:263) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
  UVM_INFO @   9874685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```