KMAC/MASKED Simulation Results

Sunday June 01 2025 00:07:48 UTC

GitHub Revision: `a4c7f98`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.566m	14.464ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.330s	23.087us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.450s	29.987us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	13.080s	4.023ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.600s	4.246ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.910s	405.574us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.450s	29.987us	20	20	100.00
		kmac_csr_aliasing	8.600s	4.246ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.030s	39.346us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.770s	37.614us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	53.881m	335.715ms	50	50	100.00
V2	burst_write	kmac_burst_write	24.231m	28.157ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	28.637m	75.252ms	5	5	100.00
		kmac_test_vectors_sha3_256	36.492m	88.530ms	5	5	100.00
		kmac_test_vectors_sha3_384	28.359m	366.377ms	5	5	100.00
		kmac_test_vectors_sha3_512	19.268m	46.396ms	5	5	100.00
		kmac_test_vectors_shake_128	42.663m	213.575ms	5	5	100.00
		kmac_test_vectors_shake_256	32.503m	235.199ms	5	5	100.00
		kmac_test_vectors_kmac	4.310s	167.641us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.670s	89.308us	5	5	100.00
V2	sideload	kmac_sideload	8.413m	89.477ms	50	50	100.00
V2	app	kmac_app	6.659m	52.654ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.267m	17.283ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.699m	25.526ms	50	50	100.00
V2	error	kmac_error	8.818m	19.987ms	49	50	98.00
V2	key_error	kmac_key_error	20.780s	14.635ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	11.250s	1.137ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	44.650s	8.482ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	6.930s	205.545us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.203m	7.122ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	1.000m	4.190ms	50	50	100.00
V2	stress_all	kmac_stress_all	52.191m	171.818ms	50	50	100.00
V2	intr_test	kmac_intr_test	2.300s	65.974us	50	50	100.00
V2	alert_test	kmac_alert_test	2.350s	72.481us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.700s	2.008ms	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.700s	2.008ms	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.330s	23.087us	5	5	100.00
		kmac_csr_rw	2.450s	29.987us	20	20	100.00
		kmac_csr_aliasing	8.600s	4.246ms	5	5	100.00
		kmac_same_csr_outstanding	4.010s	92.325us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.330s	23.087us	5	5	100.00
		kmac_csr_rw	2.450s	29.987us	20	20	100.00
		kmac_csr_aliasing	8.600s	4.246ms	5	5	100.00
		kmac_same_csr_outstanding	4.010s	92.325us	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.980s	212.066us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.980s	212.066us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.980s	212.066us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.980s	212.066us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.190s	1.085ms	15	20	75.00
V2S	tl_intg_err	kmac_sec_cm	2.018m	8.079ms	5	5	100.00
		kmac_tl_intg_err	5.030s	797.692us	11	20	55.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.030s	797.692us	11	20	55.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.000m	4.190ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.566m	14.464ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.413m	89.477ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.980s	212.066us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	2.018m	8.079ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	2.018m	8.079ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	2.018m	8.079ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.566m	14.464ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.000m	4.190ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	2.018m	8.079ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.128m	25.082ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.566m	14.464ms	50	50	100.00
V2S		TOTAL			61	75	81.33
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.007m	16.061ms	2	10	20.00
V3		TOTAL			2	10	20.00
		TOTAL			917	940	97.55

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.44	99.14	94.47	99.89	80.28	97.09	99.38	97.86

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 14 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 5 failures.

0.kmac_shadow_reg_errors_with_csr_rw.44896924081776167181863988482208219630727558842075107656871932724651198712858
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[39] & 'hffffffff)))'
  UVM_ERROR @  10742589 ps: (kmac_csr_assert_fpv.sv:495) [ASSERT FAILED] prefix_0_rd_A
  UVM_INFO @  10742589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.kmac_shadow_reg_errors_with_csr_rw.62232778222459710523840386886221819090077518355375454541169746224498213618790
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[49] & 'hffffffff)))'
  UVM_ERROR @  21376806 ps: (kmac_csr_assert_fpv.sv:545) [ASSERT FAILED] prefix_10_rd_A
  UVM_INFO @  21376806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test kmac_tl_intg_err has 9 failures.

2.kmac_tl_intg_err.89530833843112455240065480824658774801185875851662866295525510472250976021268
Line 82, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/2.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[47] & 'hffffffff)))'
  UVM_ERROR @  21575316 ps: (kmac_csr_assert_fpv.sv:535) [ASSERT FAILED] prefix_8_rd_A
  UVM_INFO @  21575316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.kmac_tl_intg_err.88692598788066578000903195155325942667557635673042570021373843542384054214841
Line 82, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/3.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[43] & 'hffffffff)))'
  UVM_ERROR @  37046065 ps: (kmac_csr_assert_fpv.sv:515) [ASSERT FAILED] prefix_4_rd_A
  UVM_INFO @  37046065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 8 failures:
- Test kmac_stress_all_with_rand_reset has 8 failures.
  - 0.kmac_stress_all_with_rand_reset.104276605233348353854418626764438830624858493214792308786792223846024363155186
    Line 150, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2037039002 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 2037039002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.kmac_stress_all_with_rand_reset.80558846534857907133398300966240023552518338525014200891948302112595828586928
    Line 137, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2219431930 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 2219431930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_error has 1 failures.
  - 6.kmac_error.81495660535637562009599746286374567712759532288548094163434074208575509618460
    Line 219, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/6.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```