KMAC/UNMASKED Simulation Results

Sunday June 01 2025 00:07:48 UTC

GitHub Revision: `a4c7f98`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.188m	4.134ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.370s	36.516us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.490s	37.292us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	22.100s	9.591ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.450s	2.890ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.900s	1.349ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.490s	37.292us	20	20	100.00
		kmac_csr_aliasing	9.450s	2.890ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.070s	16.131us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.870s	78.075us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	52.186m	709.590ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.479m	30.469ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	26.720m	251.699ms	5	5	100.00
		kmac_test_vectors_sha3_256	26.985m	112.225ms	5	5	100.00
		kmac_test_vectors_sha3_384	21.618m	417.921ms	5	5	100.00
		kmac_test_vectors_sha3_512	14.695m	129.593ms	5	5	100.00
		kmac_test_vectors_shake_128	31.549m	84.785ms	5	5	100.00
		kmac_test_vectors_shake_256	30.943m	93.049ms	5	5	100.00
		kmac_test_vectors_kmac	5.840s	902.246us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.490s	324.808us	5	5	100.00
V2	sideload	kmac_sideload	5.970m	84.529ms	50	50	100.00
V2	app	kmac_app	5.182m	18.158ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.458m	155.084ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.582m	65.769ms	50	50	100.00
V2	error	kmac_error	7.663m	20.189ms	49	50	98.00
V2	key_error	kmac_key_error	12.030s	5.469ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.663m	10.017ms	35	50	70.00
V2	edn_timeout_error	kmac_edn_timeout_error	33.240s	1.747ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	43.090s	6.421ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	53.600s	15.100ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	24.540s	3.354ms	50	50	100.00
V2	stress_all	kmac_stress_all	26.060m	272.408ms	50	50	100.00
V2	intr_test	kmac_intr_test	2.310s	160.018us	50	50	100.00
V2	alert_test	kmac_alert_test	3.540s	20.910us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.900s	57.837us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.900s	57.837us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.370s	36.516us	5	5	100.00
		kmac_csr_rw	2.490s	37.292us	20	20	100.00
		kmac_csr_aliasing	9.450s	2.890ms	5	5	100.00
		kmac_same_csr_outstanding	3.610s	130.869us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.370s	36.516us	5	5	100.00
		kmac_csr_rw	2.490s	37.292us	20	20	100.00
		kmac_csr_aliasing	9.450s	2.890ms	5	5	100.00
		kmac_same_csr_outstanding	3.610s	130.869us	20	20	100.00
V2		TOTAL			724	740	97.84
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.890s	267.366us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.890s	267.366us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.890s	267.366us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.890s	267.366us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.110s	88.891us	13	20	65.00
V2S	tl_intg_err	kmac_sec_cm	1.213m	5.054ms	5	5	100.00
		kmac_tl_intg_err	4.930s	409.146us	13	20	65.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.930s	409.146us	13	20	65.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	24.540s	3.354ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.188m	4.134ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	5.970m	84.529ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.890s	267.366us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.213m	5.054ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.213m	5.054ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.213m	5.054ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.188m	4.134ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	24.540s	3.354ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.213m	5.054ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.031m	12.817ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.188m	4.134ms	50	50	100.00
V2S		TOTAL			61	75	81.33
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.710m	5.319ms	2	10	20.00
V3		TOTAL			2	10	20.00
		TOTAL			902	940	95.96

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.69	97.23	94.42	100.00	72.73	95.98	99.35	96.13

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 14 failures:

Test kmac_tl_intg_err has 7 failures.

0.kmac_tl_intg_err.26088444876052635833053968607759354818001528723261328758959712649879130284269
Line 82, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[43] & 'hffffffff)))'
  UVM_ERROR @  17383342 ps: (kmac_csr_assert_fpv.sv:515) [ASSERT FAILED] prefix_4_rd_A
  UVM_INFO @  17383342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.kmac_tl_intg_err.52382202164970929509357791748416725546233895879643822932445824412131900869461
Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/1.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[39] & 'hffffffff)))'
  UVM_ERROR @  47617227 ps: (kmac_csr_assert_fpv.sv:495) [ASSERT FAILED] prefix_0_rd_A
  UVM_INFO @  47617227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test kmac_shadow_reg_errors_with_csr_rw has 7 failures.

4.kmac_shadow_reg_errors_with_csr_rw.114020619166492696013686461633163824597293119107049443687304188751577033594848
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[42] & 'hffffffff)))'
  UVM_ERROR @  15909538 ps: (kmac_csr_assert_fpv.sv:510) [ASSERT FAILED] prefix_3_rd_A
  UVM_INFO @  15909538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.kmac_shadow_reg_errors_with_csr_rw.89926427953521068817835740799541523694892193016384773045197224074419855643946
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[48] & 'hffffffff)))'
  UVM_ERROR @  26311845 ps: (kmac_csr_assert_fpv.sv:540) [ASSERT FAILED] prefix_9_rd_A
  UVM_INFO @  26311845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 6 failures:
- Test kmac_stress_all_with_rand_reset has 6 failures.
  - 1.kmac_stress_all_with_rand_reset.2549912100131777493742158489988759908810106015953311560965549025127415899843
    Line 194, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1594823492 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 1594823492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.kmac_stress_all_with_rand_reset.18948637623035908613271521470069912182308885609979203689008916000439059961812
    Line 106, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4907759302 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 4907759302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 4 more failures.
UVM_ERROR (cip_base_vseq.sv:928) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 0.kmac_stress_all_with_rand_reset.93611961078776128545386172771363843613405586188781396154240033777120913815442
    Line 191, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14054440585 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 14054440585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.kmac_stress_all_with_rand_reset.34949001241859987180757154533412732130877032936762702630298010068642334508936
    Line 113, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1850762701 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1850762701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 2 failures:
- Test kmac_sideload_invalid has 2 failures.
  - 8.kmac_sideload_invalid.96648403771319715313401380754616471242160403182896420645379234308530211391030
    Line 74, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/8.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10113680317 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x226a6000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 10113680317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 19.kmac_sideload_invalid.50997956363770992159108809628599425212173362364103801307751361217168301720731
    Line 74, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/19.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10016914572 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xf0472000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 10016914572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 2 failures:
- Test kmac_sideload_invalid has 2 failures.
  - 9.kmac_sideload_invalid.90583699748059558135099303469390875041598770449326070984611138838423790173451
    Line 93, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/9.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10273444847 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xdacc1000, Comparison=CompareOpEq, exp_data=0x1, call_count=19)
  UVM_INFO @ 10273444847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 20.kmac_sideload_invalid.63267617197541721103343238533685955000723494364021165933040962939092266678076
    Line 92, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/20.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 11416236276 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x72703000, Comparison=CompareOpEq, exp_data=0x1, call_count=19)
  UVM_INFO @ 11416236276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 2 failures:
- Test kmac_sideload_invalid has 2 failures.
  - 14.kmac_sideload_invalid.48867623508666403590229843630754686556153640534768340954452766823012714948781
    Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/14.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10039797896 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xe025000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
  UVM_INFO @ 10039797896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 38.kmac_sideload_invalid.102137517933013558528919612265719589269411109434685840017924431407013063117092
    Line 80, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/38.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10094005307 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xd5f8a000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
  UVM_INFO @ 10094005307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 2 failures:
- Test kmac_sideload_invalid has 2 failures.
  - 44.kmac_sideload_invalid.72650855174499162078708239164230124273612454246904272315641358080323279683774
    Line 73, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/44.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10025721697 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x89ed4000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
  UVM_INFO @ 10025721697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 45.kmac_sideload_invalid.10903449282968250179992054658266687047449712123631237256754172445143446413226
    Line 73, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/45.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10014157650 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xbd377000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
  UVM_INFO @ 10014157650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 5.kmac_sideload_invalid.17643437657921478971526780211118556823572805992060653871068483967851931995388
    Line 97, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/5.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 11021480886 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x60b3d000, Comparison=CompareOpEq, exp_data=0x1, call_count=23)
  UVM_INFO @ 11021480886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 12.kmac_sideload_invalid.7564379079982306968986569146378249768569323432919272107055479820514002036724
    Line 83, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/12.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10063599854 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xdbaf3000, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
  UVM_INFO @ 10063599854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 17.kmac_sideload_invalid.97369259029431739090564789685935858508417671524091509374131640835765704706638
    Line 80, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/17.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10219758864 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x89e5c000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
  UVM_INFO @ 10219758864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_error has 1 failures.
  - 18.kmac_error.32611667690574513092143263314670617896651012408929682913260237441073617200140
    Line 167, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/18.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 28.kmac_sideload_invalid.102092740754598563806878246123198492188456321069203056055652719550958134036649
    Line 80, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/28.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10037757648 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x530ef000, Comparison=CompareOpEq, exp_data=0x1, call_count=9)
  UVM_INFO @ 10037757648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 33.kmac_sideload_invalid.93044297372385006833497859977901342208599768336885395498681316707700802767673
    Line 76, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/33.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10036956798 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x12277000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
  UVM_INFO @ 10036956798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 42.kmac_sideload_invalid.52449997902463097682790977213438549447854355336358383548776231563328660131897
    Line 77, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/42.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10071054440 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xbdac4000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
  UVM_INFO @ 10071054440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 47.kmac_sideload_invalid.52713118845493155374627479023046106689338619422297663435811349788017017927310
    Line 90, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/47.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10304568018 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x5f704000, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
  UVM_INFO @ 10304568018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```