a4c7f98| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | otbn_smoke | 15.000s | 67.929us | 1 | 1 | 100.00 |
| V1 | single_binary | otbn_single | 52.000s | 209.823us | 99 | 100 | 99.00 |
| V1 | csr_hw_reset | otbn_csr_hw_reset | 10.000s | 29.949us | 5 | 5 | 100.00 |
| V1 | csr_rw | otbn_csr_rw | 8.000s | 15.556us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otbn_csr_bit_bash | 9.000s | 81.506us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otbn_csr_aliasing | 8.000s | 67.597us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otbn_csr_mem_rw_with_rand_reset | 12.000s | 56.917us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otbn_csr_rw | 8.000s | 15.556us | 20 | 20 | 100.00 |
| otbn_csr_aliasing | 8.000s | 67.597us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otbn_mem_walk | 30.000s | 1.867ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otbn_mem_partial_access | 17.000s | 353.283us | 5 | 5 | 100.00 |
| V1 | TOTAL | 165 | 166 | 99.40 | |||
| V2 | reset_recovery | otbn_reset | 39.000s | 186.468us | 10 | 10 | 100.00 |
| V2 | multi_error | otbn_multi_err | 51.000s | 663.160us | 1 | 1 | 100.00 |
| V2 | back_to_back | otbn_multi | 1.417m | 1.218ms | 9 | 10 | 90.00 |
| V2 | stress_all | otbn_stress_all | 1.133m | 398.799us | 10 | 10 | 100.00 |
| V2 | lc_escalation | otbn_escalate | 48.000s | 640.633us | 58 | 60 | 96.67 |
| V2 | zero_state_err_urnd | otbn_zero_state_err_urnd | 12.000s | 52.243us | 5 | 5 | 100.00 |
| V2 | sw_errs_fatal_chk | otbn_sw_errs_fatal_chk | 27.000s | 367.293us | 10 | 10 | 100.00 |
| V2 | alert_test | otbn_alert_test | 8.000s | 22.749us | 50 | 50 | 100.00 |
| V2 | intr_test | otbn_intr_test | 8.000s | 17.123us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | otbn_tl_errors | 13.000s | 161.929us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otbn_tl_errors | 13.000s | 161.929us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otbn_csr_hw_reset | 10.000s | 29.949us | 5 | 5 | 100.00 |
| otbn_csr_rw | 8.000s | 15.556us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 8.000s | 67.597us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 10.000s | 39.744us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otbn_csr_hw_reset | 10.000s | 29.949us | 5 | 5 | 100.00 |
| otbn_csr_rw | 8.000s | 15.556us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 8.000s | 67.597us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 10.000s | 39.744us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 243 | 246 | 98.78 | |||
| V2S | mem_integrity | otbn_imem_err | 18.000s | 58.503us | 10 | 10 | 100.00 |
| otbn_dmem_err | 12.000s | 48.375us | 15 | 15 | 100.00 | ||
| V2S | internal_integrity | otbn_alu_bignum_mod_err | 13.000s | 248.145us | 5 | 5 | 100.00 |
| otbn_controller_ispr_rdata_err | 12.000s | 236.719us | 5 | 5 | 100.00 | ||
| otbn_mac_bignum_acc_err | 1.050m | 299.263us | 5 | 5 | 100.00 | ||
| otbn_urnd_err | 8.000s | 10.329us | 2 | 2 | 100.00 | ||
| V2S | illegal_bus_access | otbn_illegal_mem_acc | 11.000s | 43.717us | 5 | 5 | 100.00 |
| V2S | otbn_mem_gnt_acc_err | otbn_mem_gnt_acc_err | 24.000s | 10.009ms | 1 | 2 | 50.00 |
| V2S | otbn_non_sec_partial_wipe | otbn_partial_wipe | 10.000s | 25.347us | 9 | 10 | 90.00 |
| V2S | tl_intg_err | otbn_sec_cm | 3.850m | 3.635ms | 2 | 5 | 40.00 |
| otbn_tl_intg_err | 48.000s | 296.891us | 20 | 20 | 100.00 | ||
| V2S | passthru_mem_tl_intg_err | otbn_passthru_mem_tl_intg_err | 44.000s | 269.055us | 17 | 20 | 85.00 |
| V2S | prim_fsm_check | otbn_sec_cm | 3.850m | 3.635ms | 2 | 5 | 40.00 |
| V2S | prim_count_check | otbn_sec_cm | 3.850m | 3.635ms | 2 | 5 | 40.00 |
| V2S | sec_cm_mem_scramble | otbn_smoke | 15.000s | 67.929us | 1 | 1 | 100.00 |
| V2S | sec_cm_data_mem_integrity | otbn_dmem_err | 12.000s | 48.375us | 15 | 15 | 100.00 |
| V2S | sec_cm_instruction_mem_integrity | otbn_imem_err | 18.000s | 58.503us | 10 | 10 | 100.00 |
| V2S | sec_cm_bus_integrity | otbn_tl_intg_err | 48.000s | 296.891us | 20 | 20 | 100.00 |
| V2S | sec_cm_controller_fsm_global_esc | otbn_escalate | 48.000s | 640.633us | 58 | 60 | 96.67 |
| V2S | sec_cm_controller_fsm_local_esc | otbn_imem_err | 18.000s | 58.503us | 10 | 10 | 100.00 |
| otbn_dmem_err | 12.000s | 48.375us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 12.000s | 52.243us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 11.000s | 43.717us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 3.850m | 3.635ms | 2 | 5 | 40.00 | ||
| V2S | sec_cm_controller_fsm_sparse | otbn_sec_cm | 3.850m | 3.635ms | 2 | 5 | 40.00 |
| V2S | sec_cm_scramble_key_sideload | otbn_single | 52.000s | 209.823us | 99 | 100 | 99.00 |
| V2S | sec_cm_scramble_ctrl_fsm_local_esc | otbn_imem_err | 18.000s | 58.503us | 10 | 10 | 100.00 |
| otbn_dmem_err | 12.000s | 48.375us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 12.000s | 52.243us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 11.000s | 43.717us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 3.850m | 3.635ms | 2 | 5 | 40.00 | ||
| V2S | sec_cm_scramble_ctrl_fsm_sparse | otbn_sec_cm | 3.850m | 3.635ms | 2 | 5 | 40.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_global_esc | otbn_escalate | 48.000s | 640.633us | 58 | 60 | 96.67 |
| V2S | sec_cm_start_stop_ctrl_fsm_local_esc | otbn_imem_err | 18.000s | 58.503us | 10 | 10 | 100.00 |
| otbn_dmem_err | 12.000s | 48.375us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 12.000s | 52.243us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 11.000s | 43.717us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 3.850m | 3.635ms | 2 | 5 | 40.00 | ||
| V2S | sec_cm_start_stop_ctrl_fsm_sparse | otbn_sec_cm | 3.850m | 3.635ms | 2 | 5 | 40.00 |
| V2S | sec_cm_data_reg_sw_sca | otbn_single | 52.000s | 209.823us | 99 | 100 | 99.00 |
| V2S | sec_cm_ctrl_redun | otbn_ctrl_redun | 10.000s | 19.757us | 12 | 12 | 100.00 |
| V2S | sec_cm_pc_ctrl_flow_redun | otbn_pc_ctrl_flow_redun | 11.000s | 183.816us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_bus_consistency | otbn_rnd_sec_cm | 1.650m | 1.602ms | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_rng_digest | otbn_rnd_sec_cm | 1.650m | 1.602ms | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_integrity | otbn_rf_base_intg_err | 12.000s | 29.294us | 8 | 10 | 80.00 |
| V2S | sec_cm_rf_base_data_reg_sw_glitch_detect | otbn_sec_cm | 3.850m | 3.635ms | 2 | 5 | 40.00 |
| V2S | sec_cm_stack_wr_ptr_ctr_redun | otbn_sec_cm | 3.850m | 3.635ms | 2 | 5 | 40.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_integrity | otbn_rf_bignum_intg_err | 14.000s | 69.745us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_glitch_detect | otbn_sec_cm | 3.850m | 3.635ms | 2 | 5 | 40.00 |
| V2S | sec_cm_loop_stack_ctr_redun | otbn_sec_cm | 3.850m | 3.635ms | 2 | 5 | 40.00 |
| V2S | sec_cm_loop_stack_addr_integrity | otbn_stack_addr_integ_chk | 11.000s | 38.811us | 5 | 5 | 100.00 |
| V2S | sec_cm_call_stack_addr_integrity | otbn_stack_addr_integ_chk | 11.000s | 38.811us | 5 | 5 | 100.00 |
| V2S | sec_cm_start_stop_ctrl_state_consistency | otbn_sec_wipe_err | 13.000s | 51.622us | 6 | 7 | 85.71 |
| V2S | sec_cm_data_mem_sec_wipe | otbn_single | 52.000s | 209.823us | 99 | 100 | 99.00 |
| V2S | sec_cm_instruction_mem_sec_wipe | otbn_single | 52.000s | 209.823us | 99 | 100 | 99.00 |
| V2S | sec_cm_data_reg_sw_sec_wipe | otbn_single | 52.000s | 209.823us | 99 | 100 | 99.00 |
| V2S | sec_cm_write_mem_integrity | otbn_multi | 1.417m | 1.218ms | 9 | 10 | 90.00 |
| V2S | sec_cm_ctrl_flow_count | otbn_single | 52.000s | 209.823us | 99 | 100 | 99.00 |
| V2S | sec_cm_ctrl_flow_sca | otbn_single | 52.000s | 209.823us | 99 | 100 | 99.00 |
| V2S | sec_cm_data_mem_sw_noaccess | otbn_sw_no_acc | 12.000s | 153.440us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_sideload | otbn_single | 52.000s | 209.823us | 99 | 100 | 99.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | otbn_sec_cm | 3.850m | 3.635ms | 2 | 5 | 40.00 |
| V2S | TOTAL | 152 | 163 | 93.25 | |||
| V3 | stress_all_with_rand_reset | otbn_stress_all_with_rand_reset | 5.817m | 3.642ms | 4 | 10 | 40.00 |
| V3 | TOTAL | 4 | 10 | 40.00 | |||
| TOTAL | 564 | 585 | 96.41 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 99.12 | 99.65 | 96.08 | 99.73 | 93.27 | 93.66 | 100.00 | 97.97 | 100.00 |
UVM_ERROR (cip_base_vseq.sv:929) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
1.otbn_stress_all_with_rand_reset.90267440338635438610823265366928384129415176194204889456031214437010961456411
Line 500, in log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8780680283 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 8780680283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.otbn_stress_all_with_rand_reset.81726407582887585882491691964502774363976408635043041146895339934038634458088
Line 263, in log /nightly/runs/scratch/master/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1631558604 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1631558604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 4 failures:
Test otbn_multi has 1 failures.
0.otbn_multi.63116580472013314055227882427540746578664061396605448530351592566288014922
Line 167, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_multi/latest/run.log
UVM_FATAL @ 1218476925 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 1218476925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_stress_all_with_rand_reset has 1 failures.
0.otbn_stress_all_with_rand_reset.9010400681994172458744765076064765566060752609224551050202278431811063646644
Line 175, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 140645584 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 140645584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_passthru_mem_tl_intg_err has 2 failures.
4.otbn_passthru_mem_tl_intg_err.109614437612824736562141561147728414897723268171076401186455507728920916674949
Line 82, in log /nightly/runs/scratch/master/otbn-sim-xcelium/4.otbn_passthru_mem_tl_intg_err/latest/run.log
UVM_FATAL @ 2062136 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 2062136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.otbn_passthru_mem_tl_intg_err.534769799980257542682138982705798829064953232759035650511002534056761535290
Line 87, in log /nightly/runs/scratch/master/otbn-sim-xcelium/12.otbn_passthru_mem_tl_intg_err/latest/run.log
UVM_FATAL @ 22566040 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 22566040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 3 failures:
0.otbn_sec_cm.83634677357590298573298259026056710054062715617771506273499029687959883004581
Line 82, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 2557474 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 2557474 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
UVM_ERROR @ 2557474 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
UVM_INFO @ 2557474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.otbn_sec_cm.1145496490052451409162278145616761651426696223381362569681629137791464475804
Line 93, in log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 35254441 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 35254441 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
UVM_ERROR @ 35254441 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
UVM_INFO @ 35254441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Job returned non-zero exit code has 2 failures:
Test otbn_single has 1 failures.
1.otbn_single.43006079267659753209426100190368549639421103525941821721941363414375174701063
Log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_single/latest/run.log
make -f /nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='pushd /nightly/runs/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/runs/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 43006079267659753209426100190368549639421103525941821721941363414375174701063 --size 2000 --count 1 /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_single/latest/otbn-binaries' proj_root=/nightly/runs/opentitan run_cmd=xrun run_dir=/nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_single/latest run_opts='+en_cov=1 -covmodeldir /nightly/runs/scratch/master/otbn-sim-xcelium/coverage/default/1.otbn_single.2328035335 -covworkdir /nightly/runs/scratch/master/otbn-sim-xcelium/coverage -covscope default -covtest 1.otbn_single.2328035335 -covoverwrite +otbn_elf_dir=/nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_single/latest/otbn-binaries +cdc_instrumentation_enabled=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/runs/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/runs/scratch/master/otbn-sim-xcelium/default/xcelium.d -r tb +SVSEED=2328035335 +UVM_TESTNAME=otbn_base_test +UVM_TEST_SEQ=otbn_single_vseq -nowarn DSEM2009' seed=43006079267659753209426100190368549639421103525941821721941363414375174701063 sw_build_cmd=bazel sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otbn_base_test uvm_test_seq=otbn_single_vseq
[make]: pre_run
mkdir -p /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_single/latest
cd /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_single/latest && pushd /nightly/runs/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/runs/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 43006079267659753209426100190368549639421103525941821721941363414375174701063 --size 2000 --count 1 /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_single/latest/otbn-binaries
~/opentitan ~/scratch/master/otbn-sim-xcelium/1.otbn_single/latest
2025/06/01 12:54:41 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36
Test otbn_sec_wipe_err has 1 failures.
1.otbn_sec_wipe_err.36228874697052381844460312346796344847339903631019454544219895491183590275162
Log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_sec_wipe_err/latest/run.log
make -f /nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='pushd /nightly/runs/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/runs/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 36228874697052381844460312346796344847339903631019454544219895491183590275162 --size 2000 --count 1 /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_sec_wipe_err/latest/otbn-binaries' proj_root=/nightly/runs/opentitan run_cmd=xrun run_dir=/nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_sec_wipe_err/latest run_opts='+en_cov=1 -covmodeldir /nightly/runs/scratch/master/otbn-sim-xcelium/coverage/default/1.otbn_sec_wipe_err.1844475994 -covworkdir /nightly/runs/scratch/master/otbn-sim-xcelium/coverage -covscope default -covtest 1.otbn_sec_wipe_err.1844475994 -covoverwrite +otbn_elf_dir=/nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_sec_wipe_err/latest/otbn-binaries +cdc_instrumentation_enabled=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/runs/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/runs/scratch/master/otbn-sim-xcelium/default/xcelium.d -r tb +SVSEED=1844475994 +UVM_TESTNAME=otbn_base_test +UVM_TEST_SEQ=otbn_sec_wipe_err_vseq -nowarn DSEM2009' seed=36228874697052381844460312346796344847339903631019454544219895491183590275162 sw_build_cmd=bazel sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otbn_base_test uvm_test_seq=otbn_sec_wipe_err_vseq
[make]: pre_run
mkdir -p /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_sec_wipe_err/latest
cd /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_sec_wipe_err/latest && pushd /nightly/runs/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/runs/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 36228874697052381844460312346796344847339903631019454544219895491183590275162 --size 2000 --count 1 /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_sec_wipe_err/latest/otbn-binaries
~/opentitan ~/scratch/master/otbn-sim-xcelium/1.otbn_sec_wipe_err/latest
2025/06/01 12:54:53 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 2 failures:
10.otbn_escalate.71883062594962299669675368542114356568218977056601974774074645302279807413815
Line 110, in log /nightly/runs/scratch/master/otbn-sim-xcelium/10.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 15489162 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 15489162 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 15489162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.otbn_escalate.61334013560085505434032454647747260352603543813060200536515280252171928983164
Line 111, in log /nightly/runs/scratch/master/otbn-sim-xcelium/15.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 16931166 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 16931166 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 16931166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_mem_gnt_acc_err_vseq.sv:41) [otbn_mem_gnt_acc_err_vseq] timeout occurred! has 1 failures:
0.otbn_mem_gnt_acc_err.106418226987582456145615287064268940817480330260004481643335694526598008586252
Line 124, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_mem_gnt_acc_err/latest/run.log
UVM_FATAL @ 10009384214 ps: (otbn_mem_gnt_acc_err_vseq.sv:41) [uvm_test_top.env.virtual_sequencer.otbn_mem_gnt_acc_err_vseq] timeout occurred!
UVM_INFO @ 10009384214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sim_*/tb.sv,292): Assertion MatchingStatus_A has failed has 1 failures:
4.otbn_partial_wipe.69600116297644236643530990002583005558184217862085064536279076930279682667316
Line 107, in log /nightly/runs/scratch/master/otbn-sim-xcelium/4.otbn_partial_wipe/latest/run.log
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,292): (time 14675064 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 14675064 ps: (tb.sv:292) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 14675064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
7.otbn_rf_base_intg_err.84639126090056907567998275276264053047774975858127730948837720122530733950717
Line 114, in log /nightly/runs/scratch/master/otbn-sim-xcelium/7.otbn_rf_base_intg_err/latest/run.log
UVM_ERROR @ 25022499 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 25022499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:129) [otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked) has 1 failures:
8.otbn_rf_base_intg_err.48029651015751055745159763921554483908197499508902356270085110894168683636661
Line 116, in log /nightly/runs/scratch/master/otbn-sim-xcelium/8.otbn_rf_base_intg_err/latest/run.log
UVM_FATAL @ 29293871 ps: (otbn_rf_base_intg_err_vseq.sv:129) [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked)
UVM_INFO @ 29293871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
11.otbn_passthru_mem_tl_intg_err.99886870709515129930838198798847919565220533544827356763187896479804498561037
Line 97, in log /nightly/runs/scratch/master/otbn-sim-xcelium/11.otbn_passthru_mem_tl_intg_err/latest/run.log
UVM_FATAL @ 33409218 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 33409218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---