a4c7f98| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 6.000s | 125.812us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 5.000s | 15.347us | 5 | 5 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 5.000s | 14.315us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 6.000s | 64.874us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 5.000s | 32.179us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 5.000s | 33.842us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 5.000s | 14.315us | 20 | 20 | 100.00 |
| pattgen_csr_aliasing | 5.000s | 32.179us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | perf | pattgen_perf | 48.700m | 600.000ms | 26 | 50 | 52.00 |
| V2 | cnt_rollover | cnt_rollover | 1.600m | 2.635ms | 50 | 50 | 100.00 |
| V2 | error | pattgen_error | 5.000s | 17.087us | 50 | 50 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 2.946h | 1.360s | 23 | 50 | 46.00 |
| V2 | alert_test | pattgen_alert_test | 5.000s | 11.185us | 50 | 50 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 5.000s | 82.292us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 7.000s | 407.490us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 7.000s | 407.490us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 5.000s | 15.347us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 5.000s | 14.315us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 5.000s | 32.179us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 5.000s | 29.550us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 5.000s | 15.347us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 5.000s | 14.315us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 5.000s | 32.179us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 5.000s | 29.550us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 289 | 340 | 85.00 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 6.000s | 842.197us | 20 | 20 | 100.00 |
| pattgen_sec_cm | 5.000s | 297.114us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 6.000s | 842.197us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 3.000m | 5.770ms | 2 | 50 | 4.00 |
| V3 | TOTAL | 2 | 50 | 4.00 | |||
| Unmapped tests | pattgen_inactive_level | 4.467m | 10.133ms | 33 | 50 | 66.00 | |
| TOTAL | 454 | 570 | 79.65 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.80 | 100.00 | 100.00 | 100.00 | 98.50 | 96.61 | -- | 100.00 | 89.42 |
UVM_ERROR (cip_base_vseq.sv:929) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 47 failures:
0.pattgen_stress_all_with_rand_reset.5058042560236972119541287855446681009574860275967091448253295980249477501368
Line 232, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 19578731879 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 19578772623 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 19578772623 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/10
UVM_INFO @ 19579318077 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
1.pattgen_stress_all_with_rand_reset.36321400689291611326395836512073873098425339601095955356593016453817751150714
Line 110, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2082765808 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 2082959229 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2082959229 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 2084759229 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
... and 45 more failures.
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 21 failures:
1.pattgen_stress_all.90920577179034224511407584486539183628041738927972096723415910139589078692820
Line 138, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all/latest/run.log
UVM_ERROR @ 3110088792942 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10476
5.pattgen_stress_all.44888027928310522848945906166341263051526867618877212769767275639389987760679
Line 146, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/5.pattgen_stress_all/latest/run.log
UVM_ERROR @ 59253737 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10321
... and 19 more failures.
Job timed out after * minutes has 20 failures:
0.pattgen_perf.98014318514312862267183162761394995098857980490840038188672355279051772562402
Log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log
Job timed out after 60 minutes
4.pattgen_perf.11074901345210511604076994054398195417293711065733996793819250362325054853015
Log /nightly/runs/scratch/master/pattgen-sim-xcelium/4.pattgen_perf/latest/run.log
Job timed out after 60 minutes
... and 13 more failures.
11.pattgen_stress_all.20247662938571962149997812413013725919017424360605370099248724945842190642065
Log /nightly/runs/scratch/master/pattgen-sim-xcelium/11.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
14.pattgen_stress_all.110429681085402529915969626781789045994694769376765818388730859427711238506665
Log /nightly/runs/scratch/master/pattgen-sim-xcelium/14.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
... and 3 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 9 failures:
6.pattgen_perf.73507902105209012335416150031519270821104644964010977305539085738038639489004
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/6.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.pattgen_perf.22740276844065864298414293423650510918826878401665969898179934007734903875819
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/21.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 5 failures:
19.pattgen_inactive_level.94350887948021935244718959775561750116624256969398341850519451307237715313774
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/19.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10011821818 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x9e178710, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
UVM_INFO @ 10011821818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.pattgen_inactive_level.107280955517893947565679839844141067991257370410512149935185183812062761598672
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/33.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10056510970 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xf4377650, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
UVM_INFO @ 10056510970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 2 failures:
7.pattgen_inactive_level.106114651282604071382390226745804055049630508373262304438369668527505337905917
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/7.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10002058186 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x8860d350, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
UVM_INFO @ 10002058186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.pattgen_inactive_level.49032940357084673637351032749665210017227500750009985490361031665759518998340
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/28.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10002368818 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x3eafb690, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
UVM_INFO @ 10002368818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (pattgen_scoreboard.sv:263) scoreboard [scoreboard] has 2 failures:
Test pattgen_stress_all has 1 failures.
9.pattgen_stress_all.26673239464566865735698101625082850523216976655045175983880181709675014111845
Line 115, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/9.pattgen_stress_all/latest/run.log
UVM_ERROR @ 30188776 ps: (pattgen_scoreboard.sv:263) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 0 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
Test pattgen_stress_all_with_rand_reset has 1 failures.
47.pattgen_stress_all_with_rand_reset.112097419659768089394530445562533690868983415128474219905138026848388244734919
Line 128, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/47.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 224489799 ps: (pattgen_scoreboard.sv:263) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 1 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 2 failures:
22.pattgen_inactive_level.51328709373848024311141463641991773272655942096933449362710000910024879067136
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/22.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10120577840 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x41ae7bd0, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 10120577840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
46.pattgen_inactive_level.37519904493978558725086950501334763983723794719659385592124228126444288425108
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/46.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10075861641 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xfc742950, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 10075861641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
2.pattgen_inactive_level.65778914292432261902778237760416037504459856435697754141093670194031412019149
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/2.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10031725192 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x544e2310, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
UVM_INFO @ 10031725192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
4.pattgen_inactive_level.53461469865983571728528940453930681673473551177669921557052607768456943570798
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/4.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10047333097 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x54a46ad0, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
UVM_INFO @ 10047333097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:
9.pattgen_inactive_level.19080977072740516876660088877230615843308703208209502064229926145113609225460
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/9.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10004207546 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x53c94790, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
UVM_INFO @ 10004207546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
16.pattgen_inactive_level.66586724404372331065066677507767939494144830245980527225433032043859997878182
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/16.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10011537422 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x326ee0d0, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
UVM_INFO @ 10011537422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 1 failures:
17.pattgen_inactive_level.44233694003986312153585995926545563104163371384746604017660345399332311850743
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/17.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10012379346 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x92905410, Comparison=CompareOpEq, exp_data=0x0, call_count=4)
UVM_INFO @ 10012379346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:
26.pattgen_inactive_level.80931229751734365258222075040243924080848770614221624401653414309701862454005
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/26.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10037009163 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x79e6add0, Comparison=CompareOpEq, exp_data=0x0, call_count=16)
UVM_INFO @ 10037009163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
40.pattgen_inactive_level.90624386558529235791801535141414800977394133737298270912678644726728413133142
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/40.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10025487890 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x84792450, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
UVM_INFO @ 10025487890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=27) has 1 failures:
41.pattgen_inactive_level.41657259056927732360646330853581752975742860896672528594062090911029601029610
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/41.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10023846631 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x2d830210, Comparison=CompareOpEq, exp_data=0x0, call_count=27)
UVM_INFO @ 10023846631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---