ROM_CTRL/32KB Simulation Results

Sunday June 01 2025 00:07:48 UTC

GitHub Revision: a4c7f98

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	8.370s	134.884us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	8.610s	170.856us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	7.520s	298.996us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	6.360s	168.504us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	9.170s	536.178us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	7.930s	320.314us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	7.520s	298.996us	20	20	100.00
		rom_ctrl_csr_aliasing	9.170s	536.178us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	8.990s	551.021us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	8.240s	166.216us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	7.710s	231.731us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	31.070s	6.329ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	10.400s	301.221us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	10.160s	548.232us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	14.090s	193.126us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	14.090s	193.126us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	8.610s	170.856us	5	5	100.00
		rom_ctrl_csr_rw	7.520s	298.996us	20	20	100.00
		rom_ctrl_csr_aliasing	9.170s	536.178us	5	5	100.00
		rom_ctrl_same_csr_outstanding	9.510s	616.715us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	8.610s	170.856us	5	5	100.00
		rom_ctrl_csr_rw	7.520s	298.996us	20	20	100.00
		rom_ctrl_csr_aliasing	9.170s	536.178us	5	5	100.00
		rom_ctrl_same_csr_outstanding	9.510s	616.715us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	2.126m	2.770ms	19	20	95.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	39.930s	3.162ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.330m	573.034us	5	5	100.00
		rom_ctrl_tl_intg_err	1.241m	260.218us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.330m	573.034us	5	5	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	4.330m	573.034us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.126m	2.770ms	19	20	95.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.126m	2.770ms	19	20	95.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.126m	2.770ms	19	20	95.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.126m	2.770ms	19	20	95.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.126m	2.770ms	19	20	95.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.330m	573.034us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.330m	573.034us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	8.370s	134.884us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	8.370s	134.884us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	8.370s	134.884us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.241m	260.218us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.126m	2.770ms	19	20	95.00
		rom_ctrl_kmac_err_chk	10.400s	301.221us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	2.126m	2.770ms	19	20	95.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.126m	2.770ms	19	20	95.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	2.126m	2.770ms	19	20	95.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	39.930s	3.162ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.330m	573.034us	5	5	100.00
V2S		TOTAL			64	65	98.46
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	10.273m	19.123ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			265	266	99.62

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.67	100.00	99.41	100.00	100.00	100.00	98.98	99.28

Failure Buckets

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 1 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 7.rom_ctrl_corrupt_sig_fatal_chk.108565562804483715286472187223136947637000713388578988062281479480819563730582
      Line 93, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 8338002798 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 8338002798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---