RV_TIMER Simulation Results

Sunday June 01 2025 00:07:48 UTC

GitHub Revision: a4c7f98

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	2.170s	60.422us	20	20	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	2.130s	30.448us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	2.120s	60.784us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	5.350s	2.528ms	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	2.280s	32.117us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	2.970s	111.421us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	2.120s	60.784us	20	20	100.00
		rv_timer_csr_aliasing	2.280s	32.117us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	random_reset	rv_timer_random_reset	15.290s	71.008ms	20	20	100.00
V2	disabled	rv_timer_disabled	5.200s	1.531ms	20	20	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	12.865m	1.328s	10	10	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	12.865m	1.328s	10	10	100.00
V2	stress	rv_timer_stress_all	7.950s	3.935ms	20	20	100.00
V2	alert_test	rv_timer_alert_test	2.190s	20.994us	50	50	100.00
V2	intr_test	rv_timer_intr_test	2.140s	12.592us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	4.970s	63.224us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	4.970s	63.224us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	2.130s	30.448us	5	5	100.00
		rv_timer_csr_rw	2.120s	60.784us	20	20	100.00
		rv_timer_csr_aliasing	2.280s	32.117us	5	5	100.00
		rv_timer_same_csr_outstanding	2.400s	45.584us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	2.130s	30.448us	5	5	100.00
		rv_timer_csr_rw	2.120s	60.784us	20	20	100.00
		rv_timer_csr_aliasing	2.280s	32.117us	5	5	100.00
		rv_timer_same_csr_outstanding	2.400s	45.584us	20	20	100.00
V2		TOTAL			210	210	100.00
V2S	tl_intg_err	rv_timer_sec_cm	2.690s	209.793us	5	5	100.00
		rv_timer_tl_intg_err	3.140s	503.675us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	3.140s	503.675us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	1.364m	9.150ms	20	20	100.00
V3		TOTAL			20	20	100.00
	Unmapped tests	rv_timer_min	2.060s	11.839us	10	10	100.00
		rv_timer_max	2.170s	20.509us	10	10	100.00
		TOTAL			350	350	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
100.00	100.00	100.00	100.00	--	100.00	100.00	100.00