SPI_DEVICE/1R1W Simulation Results

Sunday June 01 2025 00:07:48 UTC

GitHub Revision: `a4c7f98`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	7.125m	224.022ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.760s	87.740us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.540s	41.531us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	27.150s	1.904ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	12.630s	1.840ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.840s	150.289us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.540s	41.531us	20	20	100.00
		spi_device_csr_aliasing	12.630s	1.840ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	2.000s	23.375us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.440s	87.601us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	2.410s	19.615us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	2.270s	1.786us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	2.010s	3.669us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	7.970s	246.795us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	7.970s	246.795us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	28.490s	71.608ms	50	50	100.00
		spi_device_tpm_sts_read	2.890s	203.650us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	47.370s	11.369ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	47.510s	187.034ms	50	50	100.00
		spi_device_flash_all	6.431m	334.455ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	41.980s	27.891ms	50	50	100.00
		spi_device_flash_all	6.431m	334.455ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	41.980s	27.891ms	50	50	100.00
		spi_device_flash_all	6.431m	334.455ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.431m	334.455ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	26.230s	15.786ms	50	50	100.00
		spi_device_flash_all	6.431m	334.455ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	26.230s	15.786ms	50	50	100.00
		spi_device_flash_all	6.431m	334.455ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	26.230s	15.786ms	50	50	100.00
		spi_device_flash_all	6.431m	334.455ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	26.230s	15.786ms	50	50	100.00
		spi_device_flash_all	6.431m	334.455ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	26.230s	15.786ms	50	50	100.00
		spi_device_flash_all	6.431m	334.455ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	24.540s	8.721ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.155m	15.808ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.155m	15.808ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.155m	15.808ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	48.600s	18.358ms	50	50	100.00
		spi_device_read_buffer_direct	22.120s	14.747ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.155m	15.808ms	50	50	100.00
		spi_device_flash_all	6.431m	334.455ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.431m	334.455ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.431m	334.455ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	22.400s	2.035ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	22.400s	2.035ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	7.125m	224.022ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.455m	76.236ms	50	50	100.00
V2	stress_all	spi_device_stress_all	11.738m	120.392ms	50	50	100.00
V2	alert_test	spi_device_alert_test	2.440s	15.326us	50	50	100.00
V2	intr_test	spi_device_intr_test	2.330s	12.986us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.410s	396.046us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.410s	396.046us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.760s	87.740us	5	5	100.00
		spi_device_csr_rw	3.540s	41.531us	20	20	100.00
		spi_device_csr_aliasing	12.630s	1.840ms	5	5	100.00
		spi_device_same_csr_outstanding	5.890s	819.252us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.760s	87.740us	5	5	100.00
		spi_device_csr_rw	3.540s	41.531us	20	20	100.00
		spi_device_csr_aliasing	12.630s	1.840ms	5	5	100.00
		spi_device_same_csr_outstanding	5.890s	819.252us	20	20	100.00
V2		TOTAL			940	961	97.81
V2S	tl_intg_err	spi_device_sec_cm	2.740s	1.289ms	5	5	100.00
		spi_device_tl_intg_err	22.860s	858.670us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.860s	858.670us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	8.274m	130.050ms	49	50	98.00
		TOTAL			1129	1151	98.09

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.56	99.11	96.53	83.54	89.36	98.39	95.76	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.14001025612204776856632481747801512417306256644889709351846195767502883383356
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1708310 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[77])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1708310 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1708310 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[973])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.115142993894833881990367336461566180430609962264765379476778377719605721575633
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1116344 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[86])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1116344 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1116344 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[982])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

Test spi_device_ram_cfg has 1 failures.

0.spi_device_ram_cfg.62792100805246988548278670011107266911240082176334251039269548892098142006452
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

  UVM_ERROR @   1217768 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xaa22c [10101010001000101100] vs 0x0 [0])
  UVM_ERROR @   1259768 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc408d8 [110001000000100011011000] vs 0x0 [0])
  UVM_ERROR @   1264768 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xba912b [101110101001000100101011] vs 0x0 [0])
  UVM_ERROR @   1357768 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x684231 [11010000100001000110001] vs 0x0 [0])
  UVM_ERROR @   1382768 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7896b9 [11110001001011010111001] vs 0x0 [0])

Job timed out after * minutes has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 9.spi_device_flash_mode_ignore_cmds.95996654104760281521210680666517579297447300955429669785334165492958410316863
    Log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/9.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  Job timed out after 60 minutes
```