SPI_DEVICE/2P Simulation Results

Sunday June 01 2025 00:07:48 UTC

GitHub Revision: a4c7f98

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	11.054m	175.036ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	3.030s	159.606us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	4.190s	502.932us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	28.040s	1.932ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	19.760s	642.485us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.020s	217.284us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	4.190s	502.932us	20	20	100.00
		spi_device_csr_aliasing	19.760s	642.485us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	2.260s	11.867us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.800s	81.634us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	2.470s	18.095us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	2.690s	28.965us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	1.980s	18.206us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	10.450s	272.628us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.450s	272.628us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	30.830s	6.180ms	50	50	100.00
		spi_device_tpm_sts_read	2.690s	209.256us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	42.520s	10.708ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	37.390s	8.286ms	50	50	100.00
		spi_device_flash_all	6.635m	318.187ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	42.930s	52.160ms	50	50	100.00
		spi_device_flash_all	6.635m	318.187ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	42.930s	52.160ms	50	50	100.00
		spi_device_flash_all	6.635m	318.187ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.635m	318.187ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	36.130s	22.971ms	50	50	100.00
		spi_device_flash_all	6.635m	318.187ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	36.130s	22.971ms	50	50	100.00
		spi_device_flash_all	6.635m	318.187ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	36.130s	22.971ms	50	50	100.00
		spi_device_flash_all	6.635m	318.187ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	36.130s	22.971ms	50	50	100.00
		spi_device_flash_all	6.635m	318.187ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	36.130s	22.971ms	50	50	100.00
		spi_device_flash_all	6.635m	318.187ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	43.560s	11.655ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.655m	38.929ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.655m	38.929ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.655m	38.929ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	55.660s	3.477ms	50	50	100.00
		spi_device_read_buffer_direct	26.340s	1.831ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.655m	38.929ms	50	50	100.00
		spi_device_flash_all	6.635m	318.187ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.635m	318.187ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.635m	318.187ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	20.030s	3.827ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	20.030s	3.827ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.054m	175.036ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	10.255m	273.433ms	50	50	100.00
V2	stress_all	spi_device_stress_all	11.349m	80.447ms	50	50	100.00
V2	alert_test	spi_device_alert_test	2.340s	26.910us	50	50	100.00
V2	intr_test	spi_device_intr_test	2.480s	17.202us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.270s	192.934us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.270s	192.934us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	3.030s	159.606us	5	5	100.00
		spi_device_csr_rw	4.190s	502.932us	20	20	100.00
		spi_device_csr_aliasing	19.760s	642.485us	5	5	100.00
		spi_device_same_csr_outstanding	5.470s	221.227us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	3.030s	159.606us	5	5	100.00
		spi_device_csr_rw	4.190s	502.932us	20	20	100.00
		spi_device_csr_aliasing	19.760s	642.485us	5	5	100.00
		spi_device_same_csr_outstanding	5.470s	221.227us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	2.890s	89.107us	5	5	100.00
		spi_device_tl_intg_err	24.360s	1.587ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	24.360s	1.587ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	9.248m	338.400ms	50	50	100.00
		TOTAL			1151	1151	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.19	99.17	96.62	87.74	89.36	98.47	95.74	99.26