SPI_HOST Simulation Results

Sunday June 01 2025 00:07:48 UTC

GitHub Revision: a4c7f98

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	2.050m	23.371ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	5.000s	60.599us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	5.000s	59.315us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	6.000s	274.653us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	5.000s	61.225us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	5.000s	124.187us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	5.000s	59.315us	20	20	100.00
		spi_host_csr_aliasing	5.000s	61.225us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	45.636us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	5.000s	22.796us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	36.000s	22.972us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	39.000s	7.583ms	50	50	100.00
		spi_host_error_cmd	31.000s	28.608us	50	50	100.00
		spi_host_event	3.483m	17.380ms	50	50	100.00
V2	clock_rate	spi_host_speed	47.000s	10.023ms	49	50	98.00
V2	speed	spi_host_speed	47.000s	10.023ms	49	50	98.00
V2	chip_select_timing	spi_host_speed	47.000s	10.023ms	49	50	98.00
V2	sw_reset	spi_host_sw_reset	4.067m	22.756ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	29.000s	38.183us	50	50	100.00
V2	cpol_cpha	spi_host_speed	47.000s	10.023ms	49	50	98.00
V2	full_cycle	spi_host_speed	47.000s	10.023ms	49	50	98.00
V2	duplex	spi_host_smoke	2.050m	23.371ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	2.050m	23.371ms	50	50	100.00
V2	stress_all	spi_host_stress_all	56.000s	1.636ms	49	50	98.00
V2	spien	spi_host_spien	3.750m	16.547ms	50	50	100.00
V2	stall	spi_host_status_stall	38.717m	292.957ms	49	50	98.00
V2	Idlecsbactive	spi_host_idlecsbactive	44.000s	11.841ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	39.000s	7.583ms	50	50	100.00
V2	alert_test	spi_host_alert_test	16.000s	31.240us	50	50	100.00
V2	intr_test	spi_host_intr_test	5.000s	21.118us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	7.000s	303.917us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	7.000s	303.917us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	5.000s	60.599us	5	5	100.00
		spi_host_csr_rw	5.000s	59.315us	20	20	100.00
		spi_host_csr_aliasing	5.000s	61.225us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	27.491us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	5.000s	60.599us	5	5	100.00
		spi_host_csr_rw	5.000s	59.315us	20	20	100.00
		spi_host_csr_aliasing	5.000s	61.225us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	27.491us	20	20	100.00
V2		TOTAL			687	690	99.57
V2S	tl_intg_err	spi_host_tl_intg_err	5.000s	210.687us	20	20	100.00
		spi_host_sec_cm	22.000s	141.954us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	5.000s	210.687us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	8.700m	30.777ms	10	10	100.00
		TOTAL			837	840	99.64

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.27	96.78	93.27	98.69	94.36	88.02	100.00	97.29	90.42

Failure Buckets

• UVM_FATAL (spi_host_base_vseq.sv:234) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* has 2 failures:

  • Test spi_host_stress_all has 1 failures.

    • 10.spi_host_stress_all.39279265633095792134050492266473848271800848218893335995967052422179362592728
      Line 272, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/10.spi_host_stress_all/latest/run.log

        UVM_FATAL @ 10063178384 ps: (spi_host_base_vseq.sv:234) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0xcf2d8e14, Comparison=CompareOpEq, exp_data=0x0, call_count=40
        UVM_INFO @ 10063178384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test spi_host_speed has 1 failures.

    • 40.spi_host_speed.100338482447394344300259914071240747452756420843435782131844904732289300876098
      Line 286, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/40.spi_host_speed/latest/run.log

        UVM_FATAL @ 10023270375 ps: (spi_host_base_vseq.sv:234) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0x6fa51214, Comparison=CompareOpEq, exp_data=0x0, call_count=51
        UVM_INFO @ 10023270375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test spi_host_status_stall has 1 failures.

    • 45.spi_host_status_stall.58622928336844715147760763096377093211422835551879269991488697205512875828592
      Line 891, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/45.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---