SRAM_CTRL/MAIN Simulation Results

Sunday June 01 2025 00:07:48 UTC

GitHub Revision: a4c7f98

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.662m	1.046ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.200s	39.728us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.310s	15.300us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.010s	163.934us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.380s	21.821us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	6.990s	1.477ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.310s	15.300us	20	20	100.00
		sram_ctrl_csr_aliasing	2.380s	21.821us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.306m	57.595ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.103m	10.467ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	27.235m	154.516ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.611m	6.591ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	43.549m	629.569ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	21.277m	22.077ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.480m	167.275ms	50	50	100.00
V2	executable	sram_ctrl_executable	24.947m	97.206ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.986m	1.486ms	50	50	100.00
		sram_ctrl_partial_access_b2b	12.103m	280.620ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.808m	3.073ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.751m	819.391us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.783m	5.094ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	16.538m	30.716ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	6.110s	3.746ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.020h	5.414s	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.270s	36.388us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	6.710s	634.701us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	6.710s	634.701us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.200s	39.728us	5	5	100.00
		sram_ctrl_csr_rw	2.310s	15.300us	20	20	100.00
		sram_ctrl_csr_aliasing	2.380s	21.821us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.430s	32.795us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.200s	39.728us	5	5	100.00
		sram_ctrl_csr_rw	2.310s	15.300us	20	20	100.00
		sram_ctrl_csr_aliasing	2.380s	21.821us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.430s	32.795us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	56.730s	28.151ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.340s	56.412us	0	5	0.00
		sram_ctrl_tl_intg_err	5.110s	370.273us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.340s	56.412us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	5.110s	370.273us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	16.538m	30.716ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	16.538m	30.716ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.310s	15.300us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	24.947m	97.206ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	24.947m	97.206ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	24.947m	97.206ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.480m	167.275ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	10.750s	13.310ms	45	50	90.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	56.730s	28.151ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	11.210s	5.086ms	39	50	78.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.662m	1.046ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.662m	1.046ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	24.947m	97.206ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.340s	56.412us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.480m	167.275ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.340s	56.412us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.340s	56.412us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.662m	1.046ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.340s	56.412us	0	5	0.00
V2S		TOTAL			124	145	85.52
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.673m	8.482ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1169	1190	98.24

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	99.28	93.01	85.18	100.00	98.03	98.61	98.14

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 11 failures:

  • Test sram_ctrl_readback_err has 11 failures.

    • 1.sram_ctrl_readback_err.62942897394954513544010723311650380272622373438401840921761383941113826376594
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 697409425 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x2c) != exp (0x4f)
        UVM_INFO @ 697409425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 5.sram_ctrl_readback_err.96478939736677063076615735239357231215665576568856504359606602991059383668857
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/5.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 1390153692 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x2d) != exp (0x31)
        UVM_INFO @ 1390153692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 9 more failures.

• Offending 'reqfifo_rvalid' has 5 failures:

  • Test sram_ctrl_mubi_enc_err has 5 failures.

    • 12.sram_ctrl_mubi_enc_err.6331729652600214873980283979837190908687902253914093751472793945431391947649
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/12.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 5991586736 ps: (tlul_adapter_sram.sv:643) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 5991586736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 27.sram_ctrl_mubi_enc_err.97322712972646407971510033800091553618808786557363931504239889244118361896115
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/27.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 730504713 ps: (tlul_adapter_sram.sv:643) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 730504713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 3 failures:

  • Test sram_ctrl_sec_cm has 3 failures.

    • 1.sram_ctrl_sec_cm.5504123015256479702498386427705588928253534780026137103390875955152302517438
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  12610932 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  12610932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.sram_ctrl_sec_cm.106104203038568994179389443002158591494285278659185734343437239957660929046920
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   6209748 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   6209748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• Offending 'pend_req[d2h.d_source].pend' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.13216800480370495976527785447406108079320072368290860381084665611580431347148
      Line 98, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending 'pend_req[d2h.d_source].pend'
        UVM_ERROR @  56411752 ps: (tlul_assert.sv:276) [ASSERT FAILED] respMustHaveReq_A
        UVM_INFO @  56411752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 4.sram_ctrl_sec_cm.44642362979335239468843948243271635524999427233389428399042009659574115599662
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   1455700 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   1455700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---