SRAM_CTRL/RET Simulation Results

Sunday June 01 2025 00:07:48 UTC

GitHub Revision: a4c7f98

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.640m	147.997us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.020s	53.585us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.100s	80.014us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.760s	43.298us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.050s	15.652us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.900s	40.665us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.100s	80.014us	20	20	100.00
		sram_ctrl_csr_aliasing	2.050s	15.652us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	14.020s	4.429ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	9.690s	3.316ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	22.549m	17.836ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.118m	83.641ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.600m	35.558ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	20.605m	25.213ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	13.020s	954.453us	50	50	100.00
V2	executable	sram_ctrl_executable	24.669m	23.460ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.606m	3.074ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.351m	41.005ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.556m	136.096us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.532m	186.272us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.786m	581.035us	50	50	100.00
V2	regwen	sram_ctrl_regwen	19.080m	15.727ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.350s	32.031us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.134h	58.359ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.180s	18.212us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	6.210s	320.015us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	6.210s	320.015us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.020s	53.585us	5	5	100.00
		sram_ctrl_csr_rw	2.100s	80.014us	20	20	100.00
		sram_ctrl_csr_aliasing	2.050s	15.652us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.250s	31.311us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.020s	53.585us	5	5	100.00
		sram_ctrl_csr_rw	2.100s	80.014us	20	20	100.00
		sram_ctrl_csr_aliasing	2.050s	15.652us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.250s	31.311us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	5.500s	5.314ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.960s	12.602us	0	5	0.00
		sram_ctrl_tl_intg_err	3.520s	420.397us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.960s	12.602us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.520s	420.397us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	19.080m	15.727ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	19.080m	15.727ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.100s	80.014us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	24.669m	23.460ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	24.669m	23.460ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	24.669m	23.460ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	13.020s	954.453us	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.630s	57.628us	46	50	92.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	5.500s	5.314ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.600s	36.964us	36	50	72.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.640m	147.997us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.640m	147.997us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	24.669m	23.460ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.960s	12.602us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	13.020s	954.453us	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.960s	12.602us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.960s	12.602us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.640m	147.997us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.960s	12.602us	0	5	0.00
V2S		TOTAL			122	145	84.14
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	9.250m	1.644ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1167	1190	98.07

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	99.26	93.01	85.10	100.00	97.99	98.60	98.33

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 14 failures:
  • Test sram_ctrl_readback_err has 14 failures.

    • 0.sram_ctrl_readback_err.94862126117624781737136871374170675643033098152507089489100038405469312658860
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  39633279 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x4b) != exp (0x7a)
        UVM_INFO @  39633279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.sram_ctrl_readback_err.29209682192458765949912416035482445938770927170564954569180386792537487961202
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 227937844 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x28) != exp (0x67)
        UVM_INFO @ 227937844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 12 more failures.

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 4 failures:
  • Test sram_ctrl_sec_cm has 4 failures.

    • 0.sram_ctrl_sec_cm.109807890217580191177038469899076641880436379663305236380049197483753486660485
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   4008486 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   4008486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.sram_ctrl_sec_cm.55789649957684063396939054586896399553604550552500389268812548785535304205529
      Line 102, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  12602304 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  12602304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• Offending 'reqfifo_rvalid' has 4 failures:
  • Test sram_ctrl_mubi_enc_err has 4 failures.

    • 3.sram_ctrl_mubi_enc_err.61909116669440613306809910359231972079978857097090054722814328431567978247902
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  46247713 ps: (tlul_adapter_sram.sv:643) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  46247713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 14.sram_ctrl_mubi_enc_err.94295317156845785280708632397319213290174259484557495192487833816221003226679
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/14.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  27037251 ps: (tlul_adapter_sram.sv:643) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  27037251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• Offending 'pend_req[d2h.d_source].pend' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 4.sram_ctrl_sec_cm.92508831085480683275667346734273549900964264773385028925291505033217502191890
      Line 96, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log

            Offending 'pend_req[d2h.d_source].pend'
        UVM_ERROR @   4895522 ps: (tlul_assert.sv:276) [ASSERT FAILED] respMustHaveReq_A
        UVM_INFO @   4895522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---