UART Simulation Results

Sunday June 01 2025 00:07:48 UTC

GitHub Revision: a4c7f98

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.096m	11.095ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	2.240s	36.301us	5	5	100.00
V1	csr_rw	uart_csr_rw	2.300s	15.597us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	3.800s	479.311us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	2.430s	59.045us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	2.740s	30.681us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	2.300s	15.597us	20	20	100.00
		uart_csr_aliasing	2.430s	59.045us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	6.506m	176.302ms	50	50	100.00
V2	parity	uart_smoke	1.096m	11.095ms	50	50	100.00
		uart_tx_rx	6.506m	176.302ms	50	50	100.00
V2	parity_error	uart_intr	9.542m	449.077ms	50	50	100.00
		uart_rx_parity_err	8.163m	227.946ms	50	50	100.00
V2	watermark	uart_tx_rx	6.506m	176.302ms	50	50	100.00
		uart_intr	9.542m	449.077ms	50	50	100.00
V2	fifo_full	uart_fifo_full	16.009m	105.398ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	6.260m	167.483ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	10.516m	121.773ms	299	300	99.67
V2	rx_frame_err	uart_intr	9.542m	449.077ms	50	50	100.00
V2	rx_break_err	uart_intr	9.542m	449.077ms	50	50	100.00
V2	rx_timeout	uart_intr	9.542m	449.077ms	50	50	100.00
V2	perf	uart_perf	14.968m	18.437ms	50	50	100.00
V2	sys_loopback	uart_loopback	33.190s	13.884ms	50	50	100.00
V2	line_loopback	uart_loopback	33.190s	13.884ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	7.085m	155.530ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.511m	59.021ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	28.680s	12.946ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.137m	7.789ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	12.245m	106.379ms	48	50	96.00
V2	stress_all	uart_stress_all	20.847m	334.373ms	49	50	98.00
V2	alert_test	uart_alert_test	2.330s	31.947us	50	50	100.00
V2	intr_test	uart_intr_test	2.370s	13.360us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	3.720s	177.394us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	3.720s	177.394us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	2.240s	36.301us	5	5	100.00
		uart_csr_rw	2.300s	15.597us	20	20	100.00
		uart_csr_aliasing	2.430s	59.045us	5	5	100.00
		uart_same_csr_outstanding	2.420s	32.954us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	2.240s	36.301us	5	5	100.00
		uart_csr_rw	2.300s	15.597us	20	20	100.00
		uart_csr_aliasing	2.430s	59.045us	5	5	100.00
		uart_same_csr_outstanding	2.420s	32.954us	20	20	100.00
V2		TOTAL			1086	1090	99.63
V2S	tl_intg_err	uart_sec_cm	2.870s	727.364us	5	5	100.00
		uart_tl_intg_err	3.050s	86.891us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	3.050s	86.891us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	2.097m	8.058ms	99	100	99.00
V3		TOTAL			99	100	99.00
		TOTAL			1315	1320	99.62

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.83	99.48	98.25	91.55	--	98.14	100.00	99.55

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty has 3 failures:

  • Test uart_stress_all has 1 failures.

    • 33.uart_stress_all.34594692795623369762730434391918026985043275678631554708447194692456211157060
      Line 81, in log /nightly/runs/scratch/master/uart-sim-vcs/33.uart_stress_all/latest/run.log

        UVM_ERROR @ 140849103256 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 171621215211 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_tx_rx_vseq] finished run 1/13
        UVM_INFO @ 186959701890 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_tx_rx_vseq] finished run 2/13
        UVM_INFO @ 188920543202 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_tx_rx_vseq] finished run 3/13
        UVM_INFO @ 190616382659 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_tx_rx_vseq] finished run 4/13
      

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 46.uart_stress_all_with_rand_reset.103162444966760802975275852175115176431511388559883436282501079641511452570835
      Line 129, in log /nightly/runs/scratch/master/uart-sim-vcs/46.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3195706584 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 3356006584 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/744
        UVM_INFO @ 3535886584 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/744
        UVM_INFO @ 3711726584 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/744
        UVM_INFO @ 3829306584 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/744
      

  • Test uart_fifo_reset has 1 failures.

    • 245.uart_fifo_reset.27102207683614224453074788319341810053953531989438492233300634693835236915647
      Line 69, in log /nightly/runs/scratch/master/uart-sim-vcs/245.uart_fifo_reset/latest/run.log

        UVM_ERROR @   9896074 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 8620887463 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/10
        UVM_INFO @ 8815391459 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/10
        UVM_INFO @ 10010962996 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/10
        UVM_INFO @ 71170671067 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/10
      

• UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 1 failures:

  • Test uart_long_xfer_wo_dly has 1 failures.

    • 8.uart_long_xfer_wo_dly.104260502920982550025164444132874310239827433749146131796751103169179334266602
      Line 72, in log /nightly/runs/scratch/master/uart-sim-vcs/8.uart_long_xfer_wo_dly/latest/run.log

        UVM_ERROR @ 62263862308 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
        UVM_ERROR @ 63000985852 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
        UVM_ERROR @ 63236752444 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
        UVM_ERROR @ 63676932436 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
        UVM_ERROR @ 64240760476 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
      

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:

  • Test uart_long_xfer_wo_dly has 1 failures.

    • 20.uart_long_xfer_wo_dly.10927299732259718663459841220943359723165622751647878616986776702936989584458
      Line 75, in log /nightly/runs/scratch/master/uart-sim-vcs/20.uart_long_xfer_wo_dly/latest/run.log

        UVM_ERROR @ 159922127623 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
        UVM_INFO @ 163376861143 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 7/7
        UVM_INFO @ 196866481959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---