ADC_CTRL Simulation Results

Sunday June 08 2025 00:08:59 UTC

GitHub Revision: `2995ba4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	24.400s	6.052ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	6.550s	1.368ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	4.040s	545.686us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	2.466m	45.381ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.760s	761.474us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	4.220s	501.002us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	4.040s	545.686us	20	20	100.00
		adc_ctrl_csr_aliasing	4.760s	761.474us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	23.674m	500.925ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	16.983m	496.381ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.998m	497.349ms	49	50	98.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	18.259m	491.624ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	26.591m	628.352ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	29.247m	600.647ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	21.238m	527.090ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	27.090m	545.005ms	31	50	62.00
V2	poweron_counter	adc_ctrl_poweron_counter	19.360s	5.329ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	2.371m	38.959ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	7.634m	129.381ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	1.318h	4.316s	47	50	94.00
V2	alert_test	adc_ctrl_alert_test	3.810s	517.926us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	3.680s	470.898us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	4.900s	700.529us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	4.900s	700.529us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	6.550s	1.368ms	5	5	100.00
		adc_ctrl_csr_rw	4.040s	545.686us	20	20	100.00
		adc_ctrl_csr_aliasing	4.760s	761.474us	5	5	100.00
		adc_ctrl_same_csr_outstanding	17.430s	5.193ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	6.550s	1.368ms	5	5	100.00
		adc_ctrl_csr_rw	4.040s	545.686us	20	20	100.00
		adc_ctrl_csr_aliasing	4.760s	761.474us	5	5	100.00
		adc_ctrl_same_csr_outstanding	17.430s	5.193ms	20	20	100.00
V2		TOTAL			716	740	96.76
V2S	tl_intg_err	adc_ctrl_sec_cm	26.580s	8.023ms	5	5	100.00
		adc_ctrl_tl_intg_err	29.680s	8.055ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	29.680s	8.055ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	7.564m	10.000s	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			894	920	97.17

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.38	99.05	96.03	100.00	100.00	98.64	97.57	90.36

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 13 failures:
- Test adc_ctrl_clock_gating has 10 failures.
  - 2.adc_ctrl_clock_gating.114500611558526561321137570506665801355604706157350656679384194272980087066918
    Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/2.adc_ctrl_clock_gating/latest/run.log
```
  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.adc_ctrl_clock_gating.4035137747330738127045220109875628802515850709688284691808058464540846148986
    Line 163, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/9.adc_ctrl_clock_gating/latest/run.log
```
  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 8 more failures.
- Test adc_ctrl_filters_both has 1 failures.
  - 46.adc_ctrl_filters_both.36048719586571316697579766427145214567928624388568818325890991175529962303368
    Line 178, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/46.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test adc_ctrl_stress_all has 1 failures.
  - 47.adc_ctrl_stress_all.30107189794504946522297217253595960579006488084595349079084135668863421393587
    Line 147, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/47.adc_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 48.adc_ctrl_stress_all_with_rand_reset.80035859291335891943110028301914812577893314273921103328837017897977902953685
    Line 243, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/48.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 7 failures:

Test adc_ctrl_clock_gating has 6 failures.

6.adc_ctrl_clock_gating.91621381291223780877156949738555949194100446195490779931217365687973835359414
Line 163, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/6.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 187507448662 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 187507448662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

23.adc_ctrl_clock_gating.109432834029307592073192444228559196535080545185182282554575110890243201727316
Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/23.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 5764163731 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 5764163731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test adc_ctrl_stress_all has 1 failures.

22.adc_ctrl_stress_all.91980943357071500766934635161574013830530535809657860581654821545672172917068
Line 178, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/22.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 198718714123 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 198718714123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 5 failures:

Test adc_ctrl_clock_gating has 3 failures.

12.adc_ctrl_clock_gating.59009790542652427778593115725751679559826548032859661415230379042126024655913
Line 163, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/12.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 356343111620 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 356343111620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.adc_ctrl_clock_gating.80265254255358720646657944604343025271530949827817117190727395302123182933501
Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/27.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 161183259377 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 161183259377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test adc_ctrl_stress_all has 1 failures.

42.adc_ctrl_stress_all.91291876230430022451575156922911187842529367155963933237814854723156812549355
Line 165, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/42.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 252325621258 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 252325621258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_filters_interrupt has 1 failures.

48.adc_ctrl_filters_interrupt.62526863222484726010943478268140824486055716818701113473270791869092132063988
Line 178, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/48.adc_ctrl_filters_interrupt/latest/run.log

  UVM_ERROR @ 406737187743 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 406737187743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (adc_ctrl_scoreboard.sv:137) [scoreboard] Check failed m_wakeup == m_expected_wakeup (* [*] vs * [*]) has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 40.adc_ctrl_stress_all_with_rand_reset.18419332407669476874811270543842329439246817124231191903574847857396927731898
    Line 229, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/40.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10362305867 ps: (adc_ctrl_scoreboard.sv:137) [uvm_test_top.env.scoreboard] Check failed m_wakeup == m_expected_wakeup (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 10362305867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```