AES/MASKED Simulation Results

Sunday June 08 2025 00:08:59 UTC

GitHub Revision: `2995ba4`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	58.267us	1	1	100.00
V1	smoke	aes_smoke	10.000s	302.880us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	61.881us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	57.785us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	826.015us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	8.000s	1.480ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	75.831us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	57.785us	20	20	100.00
		aes_csr_aliasing	8.000s	1.480ms	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	10.000s	302.880us	50	50	100.00
		aes_config_error	50.000s	3.559ms	50	50	100.00
		aes_stress	12.000s	224.865us	50	50	100.00
V2	key_length	aes_smoke	10.000s	302.880us	50	50	100.00
		aes_config_error	50.000s	3.559ms	50	50	100.00
		aes_stress	12.000s	224.865us	50	50	100.00
V2	back2back	aes_stress	12.000s	224.865us	50	50	100.00
		aes_b2b	28.000s	541.758us	50	50	100.00
V2	backpressure	aes_stress	12.000s	224.865us	50	50	100.00
V2	multi_message	aes_smoke	10.000s	302.880us	50	50	100.00
		aes_config_error	50.000s	3.559ms	50	50	100.00
		aes_stress	12.000s	224.865us	50	50	100.00
		aes_alert_reset	14.000s	773.573us	50	50	100.00
V2	failure_test	aes_man_cfg_err	7.000s	215.186us	50	50	100.00
		aes_config_error	50.000s	3.559ms	50	50	100.00
		aes_alert_reset	14.000s	773.573us	50	50	100.00
V2	trigger_clear_test	aes_clear	2.067m	7.317ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	9.000s	333.372us	1	1	100.00
V2	reset_recovery	aes_alert_reset	14.000s	773.573us	50	50	100.00
V2	stress	aes_stress	12.000s	224.865us	50	50	100.00
V2	sideload	aes_stress	12.000s	224.865us	50	50	100.00
		aes_sideload	17.000s	1.360ms	50	50	100.00
V2	deinitialization	aes_deinit	20.000s	1.769ms	50	50	100.00
V2	stress_all	aes_stress_all	1.267m	4.289ms	10	10	100.00
V2	alert_test	aes_alert_test	6.000s	72.142us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	894.868us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	894.868us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	61.881us	5	5	100.00
		aes_csr_rw	5.000s	57.785us	20	20	100.00
		aes_csr_aliasing	8.000s	1.480ms	5	5	100.00
		aes_same_csr_outstanding	6.000s	171.228us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	61.881us	5	5	100.00
		aes_csr_rw	5.000s	57.785us	20	20	100.00
		aes_csr_aliasing	8.000s	1.480ms	5	5	100.00
		aes_same_csr_outstanding	6.000s	171.228us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	21.000s	1.465ms	50	50	100.00
V2S	fault_inject	aes_fi	39.000s	2.371ms	50	50	100.00
		aes_control_fi	45.000s	10.006ms	274	300	91.33
		aes_cipher_fi	47.000s	10.007ms	331	350	94.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	6.000s	286.673us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	6.000s	286.673us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	6.000s	286.673us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	6.000s	286.673us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	98.252us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	10.000s	948.609us	5	5	100.00
		aes_tl_intg_err	7.000s	508.406us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	7.000s	508.406us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	14.000s	773.573us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	6.000s	286.673us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	10.000s	302.880us	50	50	100.00
		aes_stress	12.000s	224.865us	50	50	100.00
		aes_alert_reset	14.000s	773.573us	50	50	100.00
		aes_core_fi	36.000s	10.005ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	6.000s	286.673us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	6.000s	176.899us	50	50	100.00
		aes_stress	12.000s	224.865us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	12.000s	224.865us	50	50	100.00
		aes_sideload	17.000s	1.360ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	176.899us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	176.899us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	176.899us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	176.899us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	176.899us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	12.000s	224.865us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	12.000s	224.865us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	39.000s	2.371ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	39.000s	2.371ms	50	50	100.00
		aes_control_fi	45.000s	10.006ms	274	300	91.33
		aes_cipher_fi	47.000s	10.007ms	331	350	94.57
		aes_ctr_fi	8.000s	689.459us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	39.000s	2.371ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	39.000s	2.371ms	50	50	100.00
		aes_control_fi	45.000s	10.006ms	274	300	91.33
		aes_cipher_fi	47.000s	10.007ms	331	350	94.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	47.000s	10.007ms	331	350	94.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	39.000s	2.371ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	39.000s	2.371ms	50	50	100.00
		aes_control_fi	45.000s	10.006ms	274	300	91.33
		aes_ctr_fi	8.000s	689.459us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	39.000s	2.371ms	50	50	100.00
		aes_control_fi	45.000s	10.006ms	274	300	91.33
		aes_cipher_fi	47.000s	10.007ms	331	350	94.57
		aes_ctr_fi	8.000s	689.459us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	14.000s	773.573us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	39.000s	2.371ms	50	50	100.00
		aes_control_fi	45.000s	10.006ms	274	300	91.33
		aes_cipher_fi	47.000s	10.007ms	331	350	94.57
		aes_ctr_fi	8.000s	689.459us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	39.000s	2.371ms	50	50	100.00
		aes_control_fi	45.000s	10.006ms	274	300	91.33
		aes_cipher_fi	47.000s	10.007ms	331	350	94.57
		aes_ctr_fi	8.000s	689.459us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	39.000s	2.371ms	50	50	100.00
		aes_control_fi	45.000s	10.006ms	274	300	91.33
		aes_ctr_fi	8.000s	689.459us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	39.000s	2.371ms	50	50	100.00
		aes_control_fi	45.000s	10.006ms	274	300	91.33
		aes_cipher_fi	47.000s	10.007ms	331	350	94.57
V2S		TOTAL			938	985	95.23
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	31.000s	1.642ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1545	1602	96.44

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.38	98.60	96.45	99.44	95.53	98.07	97.78	98.96	98.19

Failure Buckets

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 18 failures:
- Test aes_cipher_fi has 18 failures.
  - 29.aes_cipher_fi.61812627435066337333459238987339117360245949635957367378889438644446071555650
    Line 131, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/29.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10016562846 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016562846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 32.aes_cipher_fi.26412062058716747557224526786771488115406238876224026769691307597832088992154
    Line 148, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/32.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006231782 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006231782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 16 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 15 failures:
- Test aes_control_fi has 15 failures.
  - 5.aes_control_fi.93811729160073713362736774678176713009615803957220168460574270947682908265485
    Line 142, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/5.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10030329068 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10030329068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 11.aes_control_fi.27247213708651525396524968221537156573837535437837080553506766921655453762482
    Line 143, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/11.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10014567840 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014567840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 13 more failures.
Job timed out after * minutes has 12 failures:
- Test aes_control_fi has 11 failures.
  - 15.aes_control_fi.103693425489024802806228693342502884279112841124325670997184046016840412896247
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/15.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 18.aes_control_fi.45831170192950998993976377479832236559330335885219100519769088058906345398493
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/18.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 9 more failures.
- Test aes_cipher_fi has 1 failures.
  - 308.aes_cipher_fi.114087383223312638701355537722369549521939157865233747262410019789524001026417
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/308.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.112726146979632413838649385383494789274278594696404121702947189309760720242785
Line 479, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 958019692 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 958019692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.38403410128465458294538710729046747789931744505923329785131539185174956007666
Line 592, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1618343200 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1618343200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:

Test aes_core_fi has 2 failures.

2.aes_core_fi.31441790645773407634260685618747668882895881067514823763808064686789678807709
Line 141, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/2.aes_core_fi/latest/run.log

  UVM_FATAL @ 10024734608 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10024734608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

50.aes_core_fi.73210441831573818279845924687792017984217197651818582601017903117791359030615
Line 144, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/50.aes_core_fi/latest/run.log

  UVM_FATAL @ 10005002907 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005002907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.61857872011809273122933806448333734521513046034987244326181866686871904082007
    Line 785, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 514405210 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 514405210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:929) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.24943360679700991092273663723642481907794105027543782873238309660482901254050
    Line 270, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 280510539 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 280510539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.40928697763497694862383444306578826099177514325567495877271289109264587583566
    Line 282, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1258147152 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1258147152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```