AES/UNMASKED Simulation Results

Sunday June 08 2025 00:08:59 UTC

GitHub Revision: `2995ba4`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	42.000s	65.019us	1	1	100.00
V1	smoke	aes_smoke	6.000s	116.090us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	63.841us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	196.581us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	352.115us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	7.000s	1.491ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	6.000s	83.888us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	196.581us	20	20	100.00
		aes_csr_aliasing	7.000s	1.491ms	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	6.000s	116.090us	50	50	100.00
		aes_config_error	9.000s	439.892us	50	50	100.00
		aes_stress	7.000s	179.031us	50	50	100.00
V2	key_length	aes_smoke	6.000s	116.090us	50	50	100.00
		aes_config_error	9.000s	439.892us	50	50	100.00
		aes_stress	7.000s	179.031us	50	50	100.00
V2	back2back	aes_stress	7.000s	179.031us	50	50	100.00
		aes_b2b	13.000s	211.534us	50	50	100.00
V2	backpressure	aes_stress	7.000s	179.031us	50	50	100.00
V2	multi_message	aes_smoke	6.000s	116.090us	50	50	100.00
		aes_config_error	9.000s	439.892us	50	50	100.00
		aes_stress	7.000s	179.031us	50	50	100.00
		aes_alert_reset	7.000s	298.685us	49	50	98.00
V2	failure_test	aes_man_cfg_err	6.000s	99.837us	50	50	100.00
		aes_config_error	9.000s	439.892us	50	50	100.00
		aes_alert_reset	7.000s	298.685us	49	50	98.00
V2	trigger_clear_test	aes_clear	8.000s	84.411us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	46.000s	389.320us	1	1	100.00
V2	reset_recovery	aes_alert_reset	7.000s	298.685us	49	50	98.00
V2	stress	aes_stress	7.000s	179.031us	50	50	100.00
V2	sideload	aes_stress	7.000s	179.031us	50	50	100.00
		aes_sideload	7.000s	151.099us	50	50	100.00
V2	deinitialization	aes_deinit	24.000s	99.333us	50	50	100.00
V2	stress_all	aes_stress_all	34.000s	668.651us	10	10	100.00
V2	alert_test	aes_alert_test	6.000s	52.492us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	94.695us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	94.695us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	63.841us	5	5	100.00
		aes_csr_rw	5.000s	196.581us	20	20	100.00
		aes_csr_aliasing	7.000s	1.491ms	5	5	100.00
		aes_same_csr_outstanding	6.000s	164.510us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	63.841us	5	5	100.00
		aes_csr_rw	5.000s	196.581us	20	20	100.00
		aes_csr_aliasing	7.000s	1.491ms	5	5	100.00
		aes_same_csr_outstanding	6.000s	164.510us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	8.000s	330.811us	50	50	100.00
V2S	fault_inject	aes_fi	7.000s	221.184us	50	50	100.00
		aes_control_fi	41.000s	10.003ms	271	300	90.33
		aes_cipher_fi	45.000s	10.003ms	324	350	92.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	5.000s	122.635us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	5.000s	122.635us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	5.000s	122.635us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	5.000s	122.635us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	7.000s	124.728us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	1.210ms	5	5	100.00
		aes_tl_intg_err	8.000s	807.594us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	8.000s	807.594us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	7.000s	298.685us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	5.000s	122.635us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	6.000s	116.090us	50	50	100.00
		aes_stress	7.000s	179.031us	50	50	100.00
		aes_alert_reset	7.000s	298.685us	49	50	98.00
		aes_core_fi	4.283m	10.007ms	64	70	91.43
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	5.000s	122.635us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	6.000s	104.685us	50	50	100.00
		aes_stress	7.000s	179.031us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	7.000s	179.031us	50	50	100.00
		aes_sideload	7.000s	151.099us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	104.685us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	104.685us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	104.685us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	104.685us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	104.685us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	7.000s	179.031us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	7.000s	179.031us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	7.000s	221.184us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	7.000s	221.184us	50	50	100.00
		aes_control_fi	41.000s	10.003ms	271	300	90.33
		aes_cipher_fi	45.000s	10.003ms	324	350	92.57
		aes_ctr_fi	6.000s	52.333us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	7.000s	221.184us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	7.000s	221.184us	50	50	100.00
		aes_control_fi	41.000s	10.003ms	271	300	90.33
		aes_cipher_fi	45.000s	10.003ms	324	350	92.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	45.000s	10.003ms	324	350	92.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	7.000s	221.184us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	7.000s	221.184us	50	50	100.00
		aes_control_fi	41.000s	10.003ms	271	300	90.33
		aes_ctr_fi	6.000s	52.333us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	7.000s	221.184us	50	50	100.00
		aes_control_fi	41.000s	10.003ms	271	300	90.33
		aes_cipher_fi	45.000s	10.003ms	324	350	92.57
		aes_ctr_fi	6.000s	52.333us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	7.000s	298.685us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	7.000s	221.184us	50	50	100.00
		aes_control_fi	41.000s	10.003ms	271	300	90.33
		aes_cipher_fi	45.000s	10.003ms	324	350	92.57
		aes_ctr_fi	6.000s	52.333us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	7.000s	221.184us	50	50	100.00
		aes_control_fi	41.000s	10.003ms	271	300	90.33
		aes_cipher_fi	45.000s	10.003ms	324	350	92.57
		aes_ctr_fi	6.000s	52.333us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	7.000s	221.184us	50	50	100.00
		aes_control_fi	41.000s	10.003ms	271	300	90.33
		aes_ctr_fi	6.000s	52.333us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	7.000s	221.184us	50	50	100.00
		aes_control_fi	41.000s	10.003ms	271	300	90.33
		aes_cipher_fi	45.000s	10.003ms	324	350	92.57
V2S		TOTAL			923	985	93.71
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	26.000s	11.699ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1529	1602	95.44

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.30	97.69	94.80	98.80	93.34	98.07	91.11	98.85	98.39

Failure Buckets

Job timed out after * minutes has 29 failures:
- Test aes_ctr_fi has 1 failures.
  - 25.aes_ctr_fi.20855231730303754313931853659817741552878652690811572169923884211505509344395
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/25.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
- Test aes_cipher_fi has 11 failures.
  - 29.aes_cipher_fi.67702154421110904374573382386527121311148234657076608719836785955007495114145
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/29.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 73.aes_cipher_fi.14424013465456633662039524853200815930266336086913606021776719906106921624325
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/73.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 9 more failures.
- Test aes_control_fi has 17 failures.
  - 31.aes_control_fi.64537085961717575085348991815269241775246345830066960542198874574812765406516
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/31.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 34.aes_control_fi.38950171364433844413058595181888436005866564966148074032364938485242563802246
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/34.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 15 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 14 failures:
- Test aes_cipher_fi has 14 failures.
  - 14.aes_cipher_fi.51352860926588927404193401021378235836566983816275955528628519268301135871003
    Line 140, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/14.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10004224335 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004224335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 24.aes_cipher_fi.39129490441122514608872457430881130553091678331687117443200974691077368430649
    Line 144, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/24.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10015170513 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015170513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 12 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 12 failures:
- Test aes_control_fi has 12 failures.
  - 6.aes_control_fi.4288502204180430945034455450744586496546787735525275646769356009530249062316
    Line 130, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/6.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10009726479 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009726479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 15.aes_control_fi.12016203539022715875163721093056251792831822139640189551558967706641625080289
    Line 144, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/15.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10009470921 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009470921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 10 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.97530221015862703854778963387512478892701873282758688305473923428185600281084
Line 214, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 203226708 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 203226708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.27194659731890651140128476614788817383427177694611394750221319954407532466746
Line 891, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 557353589 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 557353589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 29.aes_core_fi.25735013738195271145168489733067761722828101701490674628361996988862250905379
    Line 138, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/29.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10003123933 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003123933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 38.aes_core_fi.25155469031880136466860669050780187853646254381928412114190289682668166839891
    Line 133, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/38.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10012032567 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012032567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 1.aes_stress_all_with_rand_reset.91195435176951989656608678415492359127359583010734553512357113210966307404709
    Line 213, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11699094422 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 11699094422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.aes_stress_all_with_rand_reset.17239829479920246641343453029282333845574478181787785587624627181024690479555
    Line 494, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2607632494 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 2607632494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 3.aes_core_fi.66641409255232551077998887481131997726627203607504778179221947997959252780252
    Line 143, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/3.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10036804148 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10036804148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 35.aes_core_fi.32777314301938361789256778283091653583203255498369415392991391047273949009397
    Line 131, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/35.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010702670 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010702670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 7.aes_stress_all_with_rand_reset.79481037250824266892727137293737079713219237698212286094071397202900935975442
    Line 404, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 133935927 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 133935927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 8.aes_stress_all_with_rand_reset.5928478886063007604070515830855635448609376073401631940324618878363711635810
    Line 148, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  16054730 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  16054730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 26.aes_core_fi.75435648312239755832772626397561192333963805669772309777139386358759458546169
    Line 135, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/26.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10007175167 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0x68e49284, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
  UVM_INFO @ 10007175167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_alert_reset has 1 failures.

30.aes_alert_reset.92788486086244408365780917026246519385558474693512194068859026206957148832588
Line 468, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/30.aes_alert_reset/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 23505137 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 23405137 PS)
  UVM_ERROR @  23505137 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  23505137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test aes_cipher_fi has 1 failures.
  - 44.aes_cipher_fi.7019910953086071747013441160218478682891172464286194102384487138637596632994
    Line 148, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/44.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```