AON_TIMER Simulation Results

Sunday June 08 2025 00:08:59 UTC

GitHub Revision: 2995ba4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	2.650s	622.959us	5	5	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	3.780s	800.323us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	2.710s	508.487us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	29.410s	13.081ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	3.470s	484.451us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	2.900s	414.980us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	2.710s	508.487us	20	20	100.00
		aon_timer_csr_aliasing	3.470s	484.451us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	2.870s	402.545us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	2.500s	457.526us	5	5	100.00
V1		TOTAL			70	70	100.00
V2	prescaler	aon_timer_prescaler	1.303m	61.946ms	15	15	100.00
V2	jump	aon_timer_jump	2.930s	674.264us	5	5	100.00
V2	stress_all	aon_timer_stress_all	1.854m	92.820ms	15	15	100.00
V2	alert_test	aon_timer_alert_test	3.260s	490.155us	50	50	100.00
V2	intr_test	aon_timer_intr_test	2.910s	375.856us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	4.180s	485.296us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	4.180s	485.296us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	3.780s	800.323us	5	5	100.00
		aon_timer_csr_rw	2.710s	508.487us	20	20	100.00
		aon_timer_csr_aliasing	3.470s	484.451us	5	5	100.00
		aon_timer_same_csr_outstanding	7.310s	2.884ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	3.780s	800.323us	5	5	100.00
		aon_timer_csr_rw	2.710s	508.487us	20	20	100.00
		aon_timer_csr_aliasing	3.470s	484.451us	5	5	100.00
		aon_timer_same_csr_outstanding	7.310s	2.884ms	20	20	100.00
V2		TOTAL			175	175	100.00
V2S	tl_intg_err	aon_timer_sec_cm	6.100s	4.370ms	5	5	100.00
		aon_timer_tl_intg_err	16.210s	8.418ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	16.210s	8.418ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	max_threshold	aon_timer_smoke_max_thold	2.930s	620.058us	5	5	100.00
V3	min_threshold	aon_timer_smoke_min_thold	3.160s	619.181us	5	5	100.00
V3	wkup_count_hi_cdc	aon_timer_wkup_count_cdc_hi	8.300s	3.358ms	5	5	100.00
V3	custom_intr	aon_timer_custom_intr	3.540s	574.919us	10	10	100.00
V3	alternating_on_off	aon_timer_alternating_enable_on_off	20.020s	4.042ms	5	5	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	51.120s	11.692ms	15	15	100.00
V3		TOTAL			45	45	100.00
		TOTAL			315	315	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.29	99.09	99.05	100.00	--	98.56	99.05	100.00