CSRNG Simulation Results

Sunday June 08 2025 00:08:59 UTC

GitHub Revision: `2995ba4`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	7.000s	129.334us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	6.000s	101.844us	5	5	100.00
V1	csr_rw	csrng_csr_rw	7.000s	103.538us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	19.000s	384.403us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	8.000s	68.697us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	8.000s	319.195us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	7.000s	103.538us	20	20	100.00
		csrng_csr_aliasing	8.000s	68.697us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	23.000s	1.025ms	163	200	81.50
V2	alerts	csrng_alert	1.083m	3.513ms	500	500	100.00
V2	err	csrng_err	7.000s	43.839us	447	500	89.40
V2	cmds	csrng_cmds	4.550m	20.770ms	50	50	100.00
V2	life cycle	csrng_cmds	4.550m	20.770ms	50	50	100.00
V2	stress_all	csrng_stress_all	14.633m	43.594ms	47	50	94.00
V2	intr_test	csrng_intr_test	6.000s	51.481us	50	50	100.00
V2	alert_test	csrng_alert_test	9.000s	130.899us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	21.000s	1.312ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	21.000s	1.312ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	6.000s	101.844us	5	5	100.00
		csrng_csr_rw	7.000s	103.538us	20	20	100.00
		csrng_csr_aliasing	8.000s	68.697us	5	5	100.00
		csrng_same_csr_outstanding	11.000s	707.972us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	6.000s	101.844us	5	5	100.00
		csrng_csr_rw	7.000s	103.538us	20	20	100.00
		csrng_csr_aliasing	8.000s	68.697us	5	5	100.00
		csrng_same_csr_outstanding	11.000s	707.972us	20	20	100.00
V2		TOTAL			1347	1440	93.54
V2S	tl_intg_err	csrng_sec_cm	12.000s	943.956us	5	5	100.00
		csrng_tl_intg_err	12.000s	435.863us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	8.000s	153.282us	50	50	100.00
		csrng_csr_rw	7.000s	103.538us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.083m	3.513ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	14.633m	43.594ms	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	23.000s	1.025ms	163	200	81.50
		csrng_err	7.000s	43.839us	447	500	89.40
		csrng_sec_cm	12.000s	943.956us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	23.000s	1.025ms	163	200	81.50
		csrng_err	7.000s	43.839us	447	500	89.40
		csrng_sec_cm	12.000s	943.956us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	23.000s	1.025ms	163	200	81.50
		csrng_err	7.000s	43.839us	447	500	89.40
		csrng_sec_cm	12.000s	943.956us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	23.000s	1.025ms	163	200	81.50
		csrng_err	7.000s	43.839us	447	500	89.40
		csrng_sec_cm	12.000s	943.956us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	23.000s	1.025ms	163	200	81.50
		csrng_err	7.000s	43.839us	447	500	89.40
		csrng_sec_cm	12.000s	943.956us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	23.000s	1.025ms	163	200	81.50
		csrng_err	7.000s	43.839us	447	500	89.40
		csrng_sec_cm	12.000s	943.956us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	23.000s	1.025ms	163	200	81.50
		csrng_err	7.000s	43.839us	447	500	89.40
		csrng_sec_cm	12.000s	943.956us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.083m	3.513ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	23.000s	1.025ms	163	200	81.50
		csrng_err	7.000s	43.839us	447	500	89.40
V2S	sec_cm_constants_lc_gated	csrng_stress_all	14.633m	43.594ms	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.083m	3.513ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	12.000s	435.863us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	23.000s	1.025ms	163	200	81.50
		csrng_err	7.000s	43.839us	447	500	89.40
		csrng_sec_cm	12.000s	943.956us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	23.000s	1.025ms	163	200	81.50
		csrng_err	7.000s	43.839us	447	500	89.40
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	23.000s	1.025ms	163	200	81.50
		csrng_err	7.000s	43.839us	447	500	89.40
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	23.000s	1.025ms	163	200	81.50
		csrng_err	7.000s	43.839us	447	500	89.40
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	23.000s	1.025ms	163	200	81.50
		csrng_err	7.000s	43.839us	447	500	89.40
		csrng_sec_cm	12.000s	943.956us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	23.000s	1.025ms	163	200	81.50
		csrng_err	7.000s	43.839us	447	500	89.40
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.350m	1.061ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1527	1630	93.68

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.59	98.53	96.44	99.86	97.36	92.15	88.00	96.31	89.83

Failure Buckets

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_cipher_control_fsm.sv,452): Assertion u_state_regs_A has failed

has 47 failures:

Test csrng_intr has 20 failures.

0.csrng_intr.58879342331039067914838036895448037770115085231670958967564661885606705871488
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_control_fsm.sv,452): (time 328721780 PS) Assertion tb.dut.u_csrng_core.u_csrng_block_encrypt.u_aes_cipher_core.u_aes_cipher_control.gen_fsm[0].gen_fsm_p.u_aes_cipher_control_fsm_i.u_aes_cipher_control_fsm.u_state_regs_A has failed
  UVM_ERROR @ 328721780 ps: (aes_cipher_control_fsm.sv:452) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @ 328721780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.csrng_intr.28206557784947297308614040287023669451339578180331345250254908052236881914080
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/3.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_control_fsm.sv,452): (time 42655781 PS) Assertion tb.dut.u_csrng_core.u_csrng_block_encrypt.u_aes_cipher_core.u_aes_cipher_control.gen_fsm[2].gen_fsm_n.u_aes_cipher_control_fsm_i.u_aes_cipher_control_fsm.u_state_regs_A has failed
  UVM_ERROR @  42655781 ps: (aes_cipher_control_fsm.sv:452) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @  42655781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 18 more failures.

Test csrng_err has 27 failures.

11.csrng_err.70810291145984155645759073729663621279674216211845343697371473332738584912081
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/11.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_control_fsm.sv,452): (time 6945562 PS) Assertion tb.dut.u_csrng_core.u_csrng_block_encrypt.u_aes_cipher_core.u_aes_cipher_control.gen_fsm[1].gen_fsm_p.u_aes_cipher_control_fsm_i.u_aes_cipher_control_fsm.u_state_regs_A has failed
  UVM_ERROR @   6945562 ps: (aes_cipher_control_fsm.sv:452) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @   6945562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

26.csrng_err.110672529359782520122528516654031812605262907020311066237888648104179777781588
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/26.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_control_fsm.sv,452): (time 7670533 PS) Assertion tb.dut.u_csrng_core.u_csrng_block_encrypt.u_aes_cipher_core.u_aes_cipher_control.gen_fsm[2].gen_fsm_n.u_aes_cipher_control_fsm_i.u_aes_cipher_control_fsm.u_state_regs_A has failed
  UVM_ERROR @   7670533 ps: (aes_cipher_control_fsm.sv:452) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @   7670533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 25 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_*/rtl/csrng_ctr_drbg_gen.sv,222): Assertion u_state_regs_A has failed

has 14 failures:

Test csrng_err has 9 failures.

5.csrng_err.29019644551915015832198388501845313479953784926509525216401310471324856238811
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/5.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_gen.sv,222): (time 2729478 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_state_regs_A has failed
  UVM_ERROR @   2729478 ps: (csrng_ctr_drbg_gen.sv:222) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @   2729478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

119.csrng_err.81264138677281729821902946688684822175760925829194294278360609586208678908023
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/119.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_gen.sv,222): (time 7940678 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_state_regs_A has failed
  UVM_ERROR @   7940678 ps: (csrng_ctr_drbg_gen.sv:222) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @   7940678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Test csrng_intr has 5 failures.

9.csrng_intr.60955776957068344691592474062211903851808660711686086140963753795641681874082
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/9.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_gen.sv,222): (time 64234813 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_state_regs_A has failed
  UVM_ERROR @  64234813 ps: (csrng_ctr_drbg_gen.sv:222) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @  64234813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

29.csrng_intr.75992229162032468115576337008906593687039890000126694098054061289693222381249
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/29.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_gen.sv,222): (time 37554738 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_state_regs_A has failed
  UVM_ERROR @  37554738 ps: (csrng_ctr_drbg_gen.sv:222) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @  37554738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_*/rtl/csrng_ctr_drbg_upd.sv,222): Assertion u_outblk_state_regs_A has failed

has 11 failures:

Test csrng_err has 8 failures.

7.csrng_err.111154914689003402179007025243930596428785234067624128060072513361989084969985
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/7.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,222): (time 2709298 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_outblk_state_regs_A has failed
  UVM_ERROR @   2709298 ps: (csrng_ctr_drbg_upd.sv:222) [ASSERT FAILED] u_outblk_state_regs_A
  UVM_INFO @   2709298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

36.csrng_err.83378367257513485570761839169876609676840514416776636727018156866093968975035
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/36.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,222): (time 2039218 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_outblk_state_regs_A has failed
  UVM_ERROR @   2039218 ps: (csrng_ctr_drbg_upd.sv:222) [ASSERT FAILED] u_outblk_state_regs_A
  UVM_INFO @   2039218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test csrng_intr has 3 failures.

24.csrng_intr.75052690014538450533204644354380585152059603339430634324428296642416316734673
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/24.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,222): (time 69816209 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_outblk_state_regs_A has failed
  UVM_ERROR @  69816209 ps: (csrng_ctr_drbg_upd.sv:222) [ASSERT FAILED] u_outblk_state_regs_A
  UVM_INFO @  69816209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

169.csrng_intr.69949519806227221375245199796228805345014810955494622265801026235342651777590
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/169.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,222): (time 157655366 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_outblk_state_regs_A has failed
  UVM_ERROR @ 157655366 ps: (csrng_ctr_drbg_upd.sv:222) [ASSERT FAILED] u_outblk_state_regs_A
  UVM_INFO @ 157655366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_*/rtl/csrng_main_sm.sv,35): Assertion u_state_regs_A has failed

has 10 failures:

Test csrng_intr has 5 failures.

59.csrng_intr.42230499193982116894060325273393753228288798255804851638267744252340429710832
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/59.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_main_sm.sv,35): (time 678728765 PS) Assertion tb.dut.u_csrng_core.u_csrng_main_sm.u_state_regs_A has failed
  UVM_ERROR @ 678728765 ps: (csrng_main_sm.sv:35) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @ 678728765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

96.csrng_intr.86279566823702395177228570286096744730283812051975661504549469553809157882949
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/96.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_main_sm.sv,35): (time 132033370 PS) Assertion tb.dut.u_csrng_core.u_csrng_main_sm.u_state_regs_A has failed
  UVM_ERROR @ 132033370 ps: (csrng_main_sm.sv:35) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @ 132033370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test csrng_err has 5 failures.

129.csrng_err.85371750795200449074874372060620083919413433589278796249471986794942330230544
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/129.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_main_sm.sv,35): (time 2191669 PS) Assertion tb.dut.u_csrng_core.u_csrng_main_sm.u_state_regs_A has failed
  UVM_ERROR @   2191669 ps: (csrng_main_sm.sv:35) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @   2191669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

166.csrng_err.18602595729577971784642179679757883029789024298218158344759379841829590422282
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/166.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_main_sm.sv,35): (time 13522558 PS) Assertion tb.dut.u_csrng_core.u_csrng_main_sm.u_state_regs_A has failed
  UVM_ERROR @  13522558 ps: (csrng_main_sm.sv:35) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @  13522558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (cip_base_vseq.sv:929) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test csrng_stress_all_with_rand_reset has 8 failures.
  - 0.csrng_stress_all_with_rand_reset.29244598404990886719423532336464283680916562782280234221207407866121484572827
    Line 110, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1133101618 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1133101618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.csrng_stress_all_with_rand_reset.25326301977951509245213693453221288523253961906051774995879372690218806232798
    Line 99, in log /nightly/runs/scratch/master/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 112768794 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 112768794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_*/rtl/csrng_ctr_drbg_upd.sv,188): Assertion u_blk_enc_state_regs_A has failed

has 8 failures:

Test csrng_err has 4 failures.

14.csrng_err.3477543687773268528306287829683263652016576503973343653151527658311393211094
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/14.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,188): (time 3814994 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_blk_enc_state_regs_A has failed
  UVM_ERROR @   3814994 ps: (csrng_ctr_drbg_upd.sv:188) [ASSERT FAILED] u_blk_enc_state_regs_A
  UVM_INFO @   3814994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

104.csrng_err.34725843971878573806961378396452443578332523189732918357004773833904083161723
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/104.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,188): (time 3815464 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_blk_enc_state_regs_A has failed
  UVM_ERROR @   3815464 ps: (csrng_ctr_drbg_upd.sv:188) [ASSERT FAILED] u_blk_enc_state_regs_A
  UVM_INFO @   3815464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test csrng_intr has 4 failures.

26.csrng_intr.21867555641627208419015020062910287958819585861265184133382536898884678319851
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/26.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,188): (time 70597781 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_blk_enc_state_regs_A has failed
  UVM_ERROR @  70597781 ps: (csrng_ctr_drbg_upd.sv:188) [ASSERT FAILED] u_blk_enc_state_regs_A
  UVM_INFO @  70597781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

37.csrng_intr.107776455370354977857947375736941038113331918829481951844804037038628872813193
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/37.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,188): (time 186943210 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_blk_enc_state_regs_A has failed
  UVM_ERROR @ 186943210 ps: (csrng_ctr_drbg_upd.sv:188) [ASSERT FAILED] u_blk_enc_state_regs_A
  UVM_INFO @ 186943210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq

has 3 failures:

Test csrng_stress_all has 3 failures.

6.csrng_stress_all.79814017165952708235852297434480346629251612476673241197655551815485789150128
Line 134, in log /nightly/runs/scratch/master/csrng-sim-xcelium/6.csrng_stress_all/latest/run.log

  UVM_ERROR @ 15625658319 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 15625658319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.csrng_stress_all.88126885348711643499071342678170919898425925323786855600063776988712590125196
Line 137, in log /nightly/runs/scratch/master/csrng-sim-xcelium/20.csrng_stress_all/latest/run.log

  UVM_ERROR @ 13945867614 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 13945867614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started has 2 failures:

Test csrng_stress_all_with_rand_reset has 2 failures.

3.csrng_stress_all_with_rand_reset.90635875893289738035068407349894864143207203203691031592427802334929949324314
Line 107, in log /nightly/runs/scratch/master/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @   8849376 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
  UVM_INFO @   8849376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.csrng_stress_all_with_rand_reset.110611978435139592748175608874364228558284348920673821168688423453337702868664
Line 140, in log /nightly/runs/scratch/master/csrng-sim-xcelium/9.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @  73079489 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
  UVM_INFO @  73079489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---