EDN Simulation Results

Sunday June 08 2025 00:08:59 UTC

GitHub Revision: 2995ba4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 2.620s 24.516us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 2.040s 16.719us 5 5 100.00
V1 csr_rw edn_csr_rw 2.640s 60.417us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 5.880s 511.107us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 2.370s 101.300us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 3.060s 162.454us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 2.640s 60.417us 20 20 100.00
edn_csr_aliasing 2.370s 101.300us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 6.230s 600.627us 300 300 100.00
V2 csrng_commands edn_genbits 6.230s 600.627us 300 300 100.00
V2 genbits edn_genbits 6.230s 600.627us 300 300 100.00
V2 interrupts edn_intr 2.830s 21.698us 50 50 100.00
V2 alerts edn_alert 2.820s 245.328us 200 200 100.00
V2 errs edn_err 2.690s 67.236us 100 100 100.00
V2 disable edn_disable 2.400s 12.203us 50 50 100.00
edn_disable_auto_req_mode 2.850s 57.073us 50 50 100.00
V2 stress_all edn_stress_all 6.630s 411.995us 50 50 100.00
V2 intr_test edn_intr_test 2.370s 45.972us 50 50 100.00
V2 alert_test edn_alert_test 2.480s 40.432us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.740s 281.779us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.740s 281.779us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 2.040s 16.719us 5 5 100.00
edn_csr_rw 2.640s 60.417us 20 20 100.00
edn_csr_aliasing 2.370s 101.300us 5 5 100.00
edn_same_csr_outstanding 2.890s 69.213us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 2.040s 16.719us 5 5 100.00
edn_csr_rw 2.640s 60.417us 20 20 100.00
edn_csr_aliasing 2.370s 101.300us 5 5 100.00
edn_same_csr_outstanding 2.890s 69.213us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 7.710s 1.023ms 5 5 100.00
edn_tl_intg_err 3.790s 130.875us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 2.400s 16.250us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 2.820s 245.328us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 7.710s 1.023ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 7.710s 1.023ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 7.710s 1.023ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 7.710s 1.023ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 2.820s 245.328us 200 200 100.00
edn_sec_cm 7.710s 1.023ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 2.820s 245.328us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 3.790s 130.875us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 1.898m 24.362ms 31 50 62.00
V3 TOTAL 31 50 62.00
TOTAL 1111 1130 98.32

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.03 98.87 94.23 97.02 93.02 96.33 99.78 92.94

Failure Buckets