ENTROPY_SRC Simulation Results

Sunday June 08 2025 00:08:59 UTC

GitHub Revision: 2995ba4

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 6.000s 37.596us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 5.000s 53.766us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 5.000s 115.676us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 14.000s 1.657ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 8.000s 833.376us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 5.000s 69.654us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 5.000s 115.676us 20 20 100.00
entropy_src_csr_aliasing 8.000s 833.376us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 6.000s 37.596us 50 50 100.00
entropy_src_rng 4.683m 12.078ms 25 300 8.33
entropy_src_fw_ov 8.467m 20.098ms 173 300 57.67
V2 firmware_mode entropy_src_fw_ov 8.467m 20.098ms 173 300 57.67
V2 rng_mode entropy_src_rng 4.683m 12.078ms 25 300 8.33
V2 rng_max_rate entropy_src_rng_max_rate 11.600m 15.025ms 8 400 2.00
V2 health_checks entropy_src_rng 4.683m 12.078ms 25 300 8.33
V2 conditioning entropy_src_rng 4.683m 12.078ms 25 300 8.33
V2 interrupts entropy_src_rng 4.683m 12.078ms 25 300 8.33
entropy_src_intr 28.000s 1.894ms 50 50 100.00
V2 alerts entropy_src_rng 4.683m 12.078ms 25 300 8.33
entropy_src_functional_alerts 7.000s 94.466us 50 50 100.00
V2 stress_all entropy_src_stress_all 8.200m 20.082ms 48 50 96.00
V2 functional_errors entropy_src_functional_errors 8.150m 10.013ms 964 1000 96.40
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 30.000s 339.484us 50 50 100.00
V2 intr_test entropy_src_intr_test 5.000s 59.785us 50 50 100.00
V2 alert_test entropy_src_alert_test 6.000s 31.954us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 7.000s 465.836us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 7.000s 465.836us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 5.000s 53.766us 5 5 100.00
entropy_src_csr_rw 5.000s 115.676us 20 20 100.00
entropy_src_csr_aliasing 8.000s 833.376us 5 5 100.00
entropy_src_same_csr_outstanding 6.000s 311.391us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 5.000s 53.766us 5 5 100.00
entropy_src_csr_rw 5.000s 115.676us 20 20 100.00
entropy_src_csr_aliasing 8.000s 833.376us 5 5 100.00
entropy_src_same_csr_outstanding 6.000s 311.391us 20 20 100.00
V2 TOTAL 1508 2340 64.44
V2S tl_intg_err entropy_src_sec_cm 6.000s 160.882us 5 5 100.00
entropy_src_tl_intg_err 7.000s 518.147us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.683m 12.078ms 25 300 8.33
entropy_src_cfg_regwen 6.000s 72.470us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.683m 12.078ms 25 300 8.33
V2S sec_cm_config_redun entropy_src_rng 4.683m 12.078ms 25 300 8.33
V2S sec_cm_intersig_mubi entropy_src_rng 4.683m 12.078ms 25 300 8.33
entropy_src_fw_ov 8.467m 20.098ms 173 300 57.67
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 8.150m 10.013ms 964 1000 96.40
entropy_src_sec_cm 6.000s 160.882us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 8.150m 10.013ms 964 1000 96.40
entropy_src_sec_cm 6.000s 160.882us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.683m 12.078ms 25 300 8.33
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 8.150m 10.013ms 964 1000 96.40
entropy_src_sec_cm 6.000s 160.882us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 8.150m 10.013ms 964 1000 96.40
entropy_src_sec_cm 6.000s 160.882us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 8.150m 10.013ms 964 1000 96.40
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 7.000s 94.466us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 7.000s 518.147us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 3.783m 10.445ms 2 50 4.00
V3 TOTAL 2 50 4.00
TOTAL 1690 2570 65.76

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
96.18 98.15 95.32 98.32 95.50 96.59 96.88 91.01 87.37

Failure Buckets