HMAC Simulation Results

Sunday June 08 2025 00:08:59 UTC

GitHub Revision: 2995ba4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	15.610s	3.377ms	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	2.500s	43.138us	5	5	100.00
V1	csr_rw	hmac_csr_rw	2.400s	60.155us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	18.110s	5.815ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	7.590s	4.195ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	9.505m	71.481ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	2.400s	60.155us	20	20	100.00
		hmac_csr_aliasing	7.590s	4.195ms	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	1.504m	17.158ms	10	10	100.00
V2	back_pressure	hmac_back_pressure	1.566m	1.655ms	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	4.458m	55.543ms	30	30	100.00
		hmac_test_sha384_vectors	9.717m	48.766ms	75	75	100.00
		hmac_test_sha512_vectors	9.350m	239.081ms	75	75	100.00
		hmac_test_hmac256_vectors	16.130s	861.343us	50	50	100.00
		hmac_test_hmac384_vectors	19.380s	1.670ms	60	60	100.00
		hmac_test_hmac512_vectors	20.330s	426.246us	75	75	100.00
V2	burst_wr	hmac_burst_wr	40.530s	782.803us	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	20.346m	28.496ms	10	10	100.00
V2	error	hmac_error	1.028m	3.687ms	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	1.536m	12.806ms	10	10	100.00
V2	save_and_restore	hmac_smoke	15.610s	3.377ms	10	10	100.00
		hmac_long_msg	1.504m	17.158ms	10	10	100.00
		hmac_back_pressure	1.566m	1.655ms	25	25	100.00
		hmac_datapath_stress	20.346m	28.496ms	10	10	100.00
		hmac_burst_wr	40.530s	782.803us	50	50	100.00
		hmac_stress_all	35.455m	145.048ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	15.610s	3.377ms	10	10	100.00
		hmac_long_msg	1.504m	17.158ms	10	10	100.00
		hmac_back_pressure	1.566m	1.655ms	25	25	100.00
		hmac_datapath_stress	20.346m	28.496ms	10	10	100.00
		hmac_wipe_secret	1.536m	12.806ms	10	10	100.00
		hmac_test_sha256_vectors	4.458m	55.543ms	30	30	100.00
		hmac_test_sha384_vectors	9.717m	48.766ms	75	75	100.00
		hmac_test_sha512_vectors	9.350m	239.081ms	75	75	100.00
		hmac_test_hmac256_vectors	16.130s	861.343us	50	50	100.00
		hmac_test_hmac384_vectors	19.380s	1.670ms	60	60	100.00
		hmac_test_hmac512_vectors	20.330s	426.246us	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	15.610s	3.377ms	10	10	100.00
		hmac_long_msg	1.504m	17.158ms	10	10	100.00
		hmac_back_pressure	1.566m	1.655ms	25	25	100.00
		hmac_datapath_stress	20.346m	28.496ms	10	10	100.00
		hmac_burst_wr	40.530s	782.803us	50	50	100.00
		hmac_error	1.028m	3.687ms	10	10	100.00
		hmac_wipe_secret	1.536m	12.806ms	10	10	100.00
		hmac_test_sha256_vectors	4.458m	55.543ms	30	30	100.00
		hmac_test_sha384_vectors	9.717m	48.766ms	75	75	100.00
		hmac_test_sha512_vectors	9.350m	239.081ms	75	75	100.00
		hmac_test_hmac256_vectors	16.130s	861.343us	50	50	100.00
		hmac_test_hmac384_vectors	19.380s	1.670ms	60	60	100.00
		hmac_test_hmac512_vectors	20.330s	426.246us	75	75	100.00
		hmac_stress_all	35.455m	145.048ms	50	50	100.00
V2	stress_all	hmac_stress_all	35.455m	145.048ms	50	50	100.00
V2	alert_test	hmac_alert_test	2.270s	15.641us	50	50	100.00
V2	intr_test	hmac_intr_test	2.220s	42.695us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	5.740s	460.180us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	5.740s	460.180us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	2.500s	43.138us	5	5	100.00
		hmac_csr_rw	2.400s	60.155us	20	20	100.00
		hmac_csr_aliasing	7.590s	4.195ms	5	5	100.00
		hmac_same_csr_outstanding	4.130s	148.993us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	2.500s	43.138us	5	5	100.00
		hmac_csr_rw	2.400s	60.155us	20	20	100.00
		hmac_csr_aliasing	7.590s	4.195ms	5	5	100.00
		hmac_same_csr_outstanding	4.130s	148.993us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	2.520s	218.820us	5	5	100.00
		hmac_tl_intg_err	6.070s	738.297us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	6.070s	738.297us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	15.610s	3.377ms	10	10	100.00
V3	stress_reset	hmac_stress_reset	8.800s	127.566us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	11.340m	94.822ms	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	3.730s	106.842us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.65	100.00	97.20	100.00	97.06	100.00	100.00	47.30