I2C Simulation Results

Sunday June 08 2025 00:08:59 UTC

GitHub Revision: `2995ba4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.568m	7.927ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	37.650s	1.539ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	2.310s	26.478us	5	5	100.00
V1	csr_rw	i2c_csr_rw	2.290s	25.563us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	5.670s	2.472ms	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	3.020s	846.185us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	3.100s	40.244us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	2.290s	25.563us	20	20	100.00
		i2c_csr_aliasing	3.020s	846.185us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	17.120s	481.450us	49	50	98.00
V2	host_stress_all	i2c_host_stress_all	42.367m	103.105ms	17	50	34.00
V2	host_maxperf	i2c_host_perf	20.782m	70.742ms	50	50	100.00
V2	host_override	i2c_host_override	2.260s	29.949us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	5.541m	10.648ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.240m	5.161ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.780s	567.453us	50	50	100.00
		i2c_host_fifo_fmt_empty	23.650s	898.809us	50	50	100.00
		i2c_host_fifo_reset_rx	12.410s	233.020us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	3.341m	7.016ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	38.460s	972.873us	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	7.580s	366.779us	17	50	34.00
V2	target_glitch	i2c_target_glitch	10.950s	17.048ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	18.274m	66.818ms	49	50	98.00
V2	target_maxperf	i2c_target_perf	10.590s	4.263ms	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	1.112m	15.792ms	50	50	100.00
		i2c_target_intr_smoke	11.500s	2.806ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	3.680s	273.383us	50	50	100.00
		i2c_target_fifo_reset_tx	3.710s	293.571us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	20.317m	63.451ms	50	50	100.00
		i2c_target_stress_rd	1.112m	15.792ms	50	50	100.00
		i2c_target_intr_stress_wr	4.096m	19.366ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	10.840s	1.434ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	2.241m	3.684ms	45	50	90.00
V2	bad_address	i2c_target_bad_addr	10.190s	1.447ms	48	50	96.00
V2	target_mode_glitch	i2c_target_hrst	36.910s	10.059ms	21	50	42.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	5.100s	2.077ms	50	50	100.00
		i2c_target_fifo_watermarks_tx	3.210s	177.814us	48	50	96.00
V2	host_mode_config_perf	i2c_host_perf	20.782m	70.742ms	50	50	100.00
		i2c_host_perf_precise	13.277m	23.225ms	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	38.460s	972.873us	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	17.690s	1.368ms	48	50	96.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	5.270s	1.074ms	50	50	100.00
		i2c_target_nack_acqfull_addr	5.150s	2.212ms	50	50	100.00
		i2c_target_nack_txstretch	3.470s	512.957us	30	50	60.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	23.360s	2.410ms	50	50	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	4.480s	907.021us	50	50	100.00
V2	alert_test	i2c_alert_test	2.240s	43.150us	50	50	100.00
V2	intr_test	i2c_intr_test	2.390s	43.113us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	3.980s	51.125us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	3.980s	51.125us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	2.310s	26.478us	5	5	100.00
		i2c_csr_rw	2.290s	25.563us	20	20	100.00
		i2c_csr_aliasing	3.020s	846.185us	5	5	100.00
		i2c_same_csr_outstanding	3.490s	709.448us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	2.310s	26.478us	5	5	100.00
		i2c_csr_rw	2.290s	25.563us	20	20	100.00
		i2c_csr_aliasing	3.020s	846.185us	5	5	100.00
		i2c_same_csr_outstanding	3.490s	709.448us	20	20	100.00
V2		TOTAL			1664	1792	92.86
V2S	tl_intg_err	i2c_tl_intg_err	3.630s	294.342us	20	20	100.00
		i2c_sec_cm	2.370s	140.356us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	3.630s	294.342us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	47.540s	5.887ms	0	10	0.00
V3	target_error_intr	i2c_target_unexp_stop	3.910s	1.619ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	8.994m	600.000ms	1	10	10.00
V3		TOTAL			1	70	1.43
		TOTAL			1845	2042	90.35

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
87.97	97.53	89.55	74.17	72.02	94.25	98.52	89.75

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 34 failures:

Test i2c_host_stress_all has 25 failures.

0.i2c_host_stress_all.48970064047007938397410347096183491890633027817205661350453201647811821869346
Line 169, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 44411662392 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @26738780

1.i2c_host_stress_all.107220710394739365271847964106197712485950190285500024060677333018107846112160
Line 179, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 6593813174 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @6517672

... and 23 more failures.

Test i2c_host_mode_toggle has 9 failures.

3.i2c_host_mode_toggle.83041515270222538710663279964820812598956273991570807247222165567966093387745
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 386038027 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @23193

6.i2c_host_mode_toggle.95452153018971655396530470029992733697020850444565923964959068342863940342330
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/6.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  79684903 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @12857

... and 7 more failures.

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 34 failures:
- Test i2c_target_unexp_stop has 33 failures.
  - 2.i2c_target_unexp_stop.8740952630614436392516777351576990053521061696151059480591045389020145490162
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  74826398 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 233 [0xe9])
  UVM_INFO @  74826398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.i2c_target_unexp_stop.95277332242548844853473892787612027510703595729354964005437695811009682063902
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  93686304 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 53 [0x35])
  UVM_INFO @  93686304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 31 more failures.
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 9.i2c_target_stress_all_with_rand_reset.70574208819771976169417703725170271272741629475842890499672954586657250081064
    Line 91, in log /nightly/runs/scratch/master/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 570763255 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 58 [0x3a])
  UVM_INFO @ 570763255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 29 failures:
- Test i2c_target_hrst has 29 failures.
  - 0.i2c_target_hrst.99344951822622168319869521117970792436870972476054395729938780590545144184726
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10120294788 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10120294788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.i2c_target_hrst.29296693541944510485795324573869542596134969737164014853840409799541236016502
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10802272995 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10802272995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 27 more failures.
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 20 failures:
- Test i2c_target_nack_txstretch has 20 failures.
  - 5.i2c_target_nack_txstretch.90639038964473012107209480285744131219069814404005959225023475801865418471149
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 237478103 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 237478103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 7.i2c_target_nack_txstretch.28983490429687449628521899819137243406490843839670727769453530732416219101108
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 165374863 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 165374863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 18 more failures.

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 18 failures:

Test i2c_host_mode_toggle has 18 failures.

7.i2c_host_mode_toggle.58813376004149738265847985393719603339468086112582441137911991444399852800012
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  65417801 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

8.i2c_host_mode_toggle.75622860225517278602485219796986794223932218537413739762708872995866293627627
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/8.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 170225290 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

... and 16 more failures.

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:

Test i2c_host_stress_all_with_rand_reset has 10 failures.

0.i2c_host_stress_all_with_rand_reset.36051655317924799684471316765355096635720985341695391921170613276636215240431
Line 91, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 264792244 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 264792244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.7065940418536139589956599737516222685861707544278399413755997046871891591989
Line 110, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4385531938 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4385531938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test i2c_target_stress_all_with_rand_reset has 7 failures.

2.i2c_target_stress_all_with_rand_reset.33489798717397452485825921137343266840740658097426156362722219084539730243419
Line 93, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3434830739 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3434830739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_target_stress_all_with_rand_reset.18488962743829538447149322975619552479490029622777454902012275186020334386734
Line 90, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 511439506 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 511439506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 11 failures:
- Test i2c_target_unexp_stop has 11 failures.
  - 0.i2c_target_unexp_stop.9174716532003959561834613211097697553507675715383023944124651855271164369011
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  58714770 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @  58714770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.i2c_target_unexp_stop.31443494658248497763977239215779403789242390742791824714172721522300327294895
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/6.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 174709688 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 174709688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 9 more failures.

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 6 failures:

Test i2c_target_unexp_stop has 6 failures.

1.i2c_target_unexp_stop.90201823068696139165031414083272707810027154598047065674858633728241176215917
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 115363827 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 115363827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_target_unexp_stop.18295150776056768338222795721406633227354526019611638945662313138879638577241
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 127608585 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 127608585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 6 failures:
- Test i2c_host_mode_toggle has 6 failures.
  - 18.i2c_host_mode_toggle.8072648251087349139699747953590895787552325798074270705297029797926278326893
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/18.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @ 131501624 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0x1de5c614, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 131501624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 32.i2c_host_mode_toggle.88142334773010574965674046581550212496623004940051644648972955262590839835042
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/32.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @  73684206 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0xd4fcde94, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @  73684206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 4 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 5 failures:
- Test i2c_target_stretch has 5 failures.
  - 7.i2c_target_stretch.30590230379990616211969950274050349587250820645895118150961820957237107901071
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10002096451 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10002096451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 26.i2c_target_stretch.37319468467229488118293306019905430984189185003618763065950706672392033694598
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/26.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10059837773 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10059837773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.

UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 5 failures:

Test i2c_host_stress_all has 5 failures.

15.i2c_host_stress_all.51715923996652716149929017959280488035989126728937508671623989910034129658180
Line 293, in log /nightly/runs/scratch/master/i2c-sim-vcs/15.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 30317116590 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @4698162

35.i2c_host_stress_all.25390868020680892564588926428473000822095776235173084460641245426965964959265
Line 304, in log /nightly/runs/scratch/master/i2c-sim-vcs/35.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 29561876220 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @7789278

... and 3 more failures.

Error-[CNST-CIF] Constraints inconsistency failure has 4 failures:

Test i2c_target_fifo_watermarks_tx has 2 failures.

7.i2c_target_fifo_watermarks_tx.83487994691712237117713536174140480527415661420781569925438689270859275258085
Line 115, in log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_target_fifo_watermarks_tx/latest/run.log

  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.

28.i2c_target_fifo_watermarks_tx.54885210103872945943550579014265404876632294343948406251436237187395295757134
Line 115, in log /nightly/runs/scratch/master/i2c-sim-vcs/28.i2c_target_fifo_watermarks_tx/latest/run.log

  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.

Test i2c_target_tx_stretch_ctrl has 2 failures.

11.i2c_target_tx_stretch_ctrl.102706229137602069440656066896966612934456355999522720694293330212932988522708
Line 118, in log /nightly/runs/scratch/master/i2c-sim-vcs/11.i2c_target_tx_stretch_ctrl/latest/run.log

  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.

24.i2c_target_tx_stretch_ctrl.101149033178709898958760045178870158021683099109941275189400035373136007105932
Line 118, in log /nightly/runs/scratch/master/i2c-sim-vcs/24.i2c_target_tx_stretch_ctrl/latest/run.log

  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.

Job timed out after * minutes has 4 failures:
- Test i2c_host_error_intr has 1 failures.
  - 11.i2c_host_error_intr.37044187034309607892605666143084529022749431037730087922436100874723639365591
    Log /nightly/runs/scratch/master/i2c-sim-vcs/11.i2c_host_error_intr/latest/run.log
```
  Job timed out after 60 minutes
```
- Test i2c_host_stress_all has 3 failures.
  - 31.i2c_host_stress_all.39566094694396274140489151128956248865072864439193450310421989308397750357080
    Log /nightly/runs/scratch/master/i2c-sim-vcs/31.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
  - 42.i2c_host_stress_all.45210562661334197035936592486466971679448383063407682051740592041568666468711
    Log /nightly/runs/scratch/master/i2c-sim-vcs/42.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 1.i2c_target_stress_all_with_rand_reset.29234950605842046599855793137498601702446283564723411930267211183313249204113
    Line 166, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_bad_addr has 2 failures.
  - 15.i2c_target_bad_addr.83471493560437853257182185284022378087815223334122926730322658051055826544258
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/15.i2c_target_bad_addr/latest/run.log
```
  UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 45.i2c_target_bad_addr.44668607843370435033005481456680898652809740784629561080611108226371729466027
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/45.i2c_target_bad_addr/latest/run.log
```
  UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 1 failures:
- Test i2c_target_stress_all has 1 failures.
  - 11.i2c_target_stress_all.88345465502662385377688800065071578558024078907673967505800646454396800927129
    Line 76, in log /nightly/runs/scratch/master/i2c-sim-vcs/11.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 10981645871 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 10981645871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```