KEYMGR Simulation Results

Sunday June 08 2025 00:08:59 UTC

GitHub Revision: `2995ba4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	36.550s	5.204ms	49	50	98.00
V1	random	keymgr_random	49.020s	2.880ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.680s	18.614us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	2.570s	28.242us	16	20	80.00
V1	csr_bit_bash	keymgr_csr_bit_bash	12.310s	5.052ms	2	5	40.00
V1	csr_aliasing	keymgr_csr_aliasing	11.440s	378.638us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	3.140s	64.714us	17	20	85.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.570s	28.242us	16	20	80.00
		keymgr_csr_aliasing	11.440s	378.638us	5	5	100.00
V1		TOTAL			144	155	92.90
V2	cfgen_during_op	keymgr_cfg_regwen	1.218m	7.181ms	50	50	100.00
V2	sideload	keymgr_sideload	17.190s	6.264ms	50	50	100.00
		keymgr_sideload_kmac	37.950s	8.903ms	50	50	100.00
		keymgr_sideload_aes	27.540s	976.192us	49	50	98.00
		keymgr_sideload_otbn	50.810s	7.059ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	38.530s	1.529ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	7.530s	2.837ms	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	7.400s	409.571us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	56.260s	7.931ms	49	50	98.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	19.280s	1.107ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	12.510s	681.285us	50	50	100.00
V2	stress_all	keymgr_stress_all	2.360m	23.926ms	50	50	100.00
V2	intr_test	keymgr_intr_test	2.330s	21.217us	50	50	100.00
V2	alert_test	keymgr_alert_test	2.470s	19.586us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.670s	599.727us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.670s	599.727us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.680s	18.614us	5	5	100.00
		keymgr_csr_rw	2.570s	28.242us	16	20	80.00
		keymgr_csr_aliasing	11.440s	378.638us	5	5	100.00
		keymgr_same_csr_outstanding	4.360s	147.266us	15	20	75.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.680s	18.614us	5	5	100.00
		keymgr_csr_rw	2.570s	28.242us	16	20	80.00
		keymgr_csr_aliasing	11.440s	378.638us	5	5	100.00
		keymgr_same_csr_outstanding	4.360s	147.266us	15	20	75.00
V2		TOTAL			733	740	99.05
V2S	sec_cm_additional_check	keymgr_sec_cm	12.930s	2.334ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	12.930s	2.334ms	5	5	100.00
		keymgr_tl_intg_err	6.910s	294.373us	15	20	75.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	6.550s	302.278us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	6.550s	302.278us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	6.550s	302.278us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	6.550s	302.278us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	9.370s	701.125us	13	20	65.00
V2S	prim_count_check	keymgr_sec_cm	12.930s	2.334ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	12.930s	2.334ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	6.910s	294.373us	15	20	75.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	6.550s	302.278us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.218m	7.181ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	49.020s	2.880ms	50	50	100.00
		keymgr_csr_rw	2.570s	28.242us	16	20	80.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	49.020s	2.880ms	50	50	100.00
		keymgr_csr_rw	2.570s	28.242us	16	20	80.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	49.020s	2.880ms	50	50	100.00
		keymgr_csr_rw	2.570s	28.242us	16	20	80.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	7.530s	2.837ms	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	19.280s	1.107ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	19.280s	1.107ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	49.020s	2.880ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	15.700s	2.157ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	12.930s	2.334ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	12.930s	2.334ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	12.930s	2.334ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	26.780s	5.584ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	7.530s	2.837ms	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	12.930s	2.334ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	12.930s	2.334ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	12.930s	2.334ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	26.780s	5.584ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	26.780s	5.584ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	12.930s	2.334ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	26.780s	5.584ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	12.930s	2.334ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	26.780s	5.584ms	50	50	100.00
V2S		TOTAL			153	165	92.73
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	24.250s	4.582ms	27	50	54.00
V3		TOTAL			27	50	54.00
		TOTAL			1057	1110	95.23

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.78	99.13	98.22	98.30	100.00	99.01	98.63	91.16

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 27 failures:

Test keymgr_tl_intg_err has 5 failures.

0.keymgr_tl_intg_err.54078571784194932425971428705364418091672983947763745553660832133887055360358
Line 95, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[13] & 'hffffffff)))'
  UVM_ERROR @  90327192 ps: (keymgr_csr_assert_fpv.sv:448) [ASSERT FAILED] attest_sw_binding_0_rd_A
  UVM_INFO @  90327192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.keymgr_tl_intg_err.60512686532391038862696126081198281798306188489896147263107733177069162009543
Line 86, in log /nightly/runs/scratch/master/keymgr-sim-vcs/4.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[18] & 'hffffffff)))'
  UVM_ERROR @  11313362 ps: (keymgr_csr_assert_fpv.sv:478) [ASSERT FAILED] attest_sw_binding_5_rd_A
  UVM_INFO @  11313362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test keymgr_csr_bit_bash has 3 failures.

0.keymgr_csr_bit_bash.68520084244600875747320895546174215614374249624791779790017420402648580589228
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[13] & 'hffffffff)))'
  UVM_ERROR @ 564730858 ps: (keymgr_csr_assert_fpv.sv:448) [ASSERT FAILED] attest_sw_binding_0_rd_A
  UVM_INFO @ 564730858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.keymgr_csr_bit_bash.32114582231356118682310354871356572099879823339497382358279003371046310910382
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[18] & 'hffffffff)))'
  UVM_ERROR @ 445418899 ps: (keymgr_csr_assert_fpv.sv:478) [ASSERT FAILED] attest_sw_binding_5_rd_A
  UVM_INFO @ 445418899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test keymgr_csr_rw has 4 failures.

1.keymgr_csr_rw.96240204886590207292204597186851861999411161450283808044574151265603773092696
Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[18] & 'hffffffff)))'
  UVM_ERROR @  19802623 ps: (keymgr_csr_assert_fpv.sv:478) [ASSERT FAILED] attest_sw_binding_5_rd_A
  UVM_INFO @  19802623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.keymgr_csr_rw.8914883105390714353868549253764139595544366194889983481058789657482850559547
Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/7.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[14] & 'hffffffff)))'
  UVM_ERROR @  15261190 ps: (keymgr_csr_assert_fpv.sv:454) [ASSERT FAILED] attest_sw_binding_1_rd_A
  UVM_INFO @  15261190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test keymgr_same_csr_outstanding has 5 failures.

2.keymgr_same_csr_outstanding.53283822198125703931041224062577107722421914012096394073250697337422898740913
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[6] & 'hffffffff)))'
  UVM_ERROR @  17178680 ps: (keymgr_csr_assert_fpv.sv:406) [ASSERT FAILED] sealing_sw_binding_1_rd_A
  UVM_INFO @  17178680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.keymgr_same_csr_outstanding.97581654601190107494404813795280974401213544077993812992631386504340136501994
Line 79, in log /nightly/runs/scratch/master/keymgr-sim-vcs/7.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[15] & 'hffffffff)))'
  UVM_ERROR @ 145109055 ps: (keymgr_csr_assert_fpv.sv:460) [ASSERT FAILED] attest_sw_binding_2_rd_A
  UVM_INFO @ 145109055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test keymgr_shadow_reg_errors_with_csr_rw has 7 failures.

3.keymgr_shadow_reg_errors_with_csr_rw.103380886239036392558774968406690432244089622098906507068653952376813819618868
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[5] & 'hffffffff)))'
  UVM_ERROR @  10105419 ps: (keymgr_csr_assert_fpv.sv:400) [ASSERT FAILED] sealing_sw_binding_0_rd_A
  UVM_INFO @  10105419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.keymgr_shadow_reg_errors_with_csr_rw.84871760497364532003957775565915117446548885347921990500229677261256402848370
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/7.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[11] & 'hffffffff)))'
  UVM_ERROR @  11044892 ps: (keymgr_csr_assert_fpv.sv:436) [ASSERT FAILED] sealing_sw_binding_6_rd_A
  UVM_INFO @  11044892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

... and 1 more tests.

UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
- Test keymgr_stress_all_with_rand_reset has 23 failures.
  - 1.keymgr_stress_all_with_rand_reset.8854880172027860074592168858233237255538777280321999776577262944883328220853
    Line 153, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 112900520 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 112900520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.keymgr_stress_all_with_rand_reset.73229081857972566338063347608244738065009607640628088592302696226649826888587
    Line 128, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 106591812 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 106591812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 21 more failures.

UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 3 failures:

Test keymgr_smoke has 1 failures.

11.keymgr_smoke.69549787346470099208524014819989856120075465648707788894282865162955351344958
Line 109, in log /nightly/runs/scratch/master/keymgr-sim-vcs/11.keymgr_smoke/latest/run.log

  UVM_ERROR @  35258893 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  35258893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_sw_invalid_input has 1 failures.

23.keymgr_sw_invalid_input.86426344376946653472405161504535313979466350887682819643714141651143764527464
Line 160, in log /nightly/runs/scratch/master/keymgr-sim-vcs/23.keymgr_sw_invalid_input/latest/run.log

  UVM_ERROR @  23626395 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  23626395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_sideload_aes has 1 failures.

33.keymgr_sideload_aes.67701634574438189600583864356465138672257196795257448734153191915359506100146
Line 85, in log /nightly/runs/scratch/master/keymgr-sim-vcs/33.keymgr_sideload_aes/latest/run.log

  UVM_ERROR @   5091552 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @   5091552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---