KMAC/MASKED Simulation Results

Sunday June 08 2025 00:08:59 UTC

GitHub Revision: `2995ba4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.471m	5.009ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.610s	201.998us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.740s	31.309us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	18.870s	5.221ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.620s	1.920ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.680s	372.309us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.740s	31.309us	20	20	100.00
		kmac_csr_aliasing	10.620s	1.920ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.200s	22.666us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.920s	66.541us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	57.130m	138.887ms	50	50	100.00
V2	burst_write	kmac_burst_write	25.325m	142.973ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	27.504m	74.700ms	5	5	100.00
		kmac_test_vectors_sha3_256	34.520m	361.975ms	5	5	100.00
		kmac_test_vectors_sha3_384	31.381m	317.163ms	5	5	100.00
		kmac_test_vectors_sha3_512	20.365m	188.118ms	5	5	100.00
		kmac_test_vectors_shake_128	35.860m	73.961ms	5	5	100.00
		kmac_test_vectors_shake_256	35.320m	347.887ms	5	5	100.00
		kmac_test_vectors_kmac	4.380s	90.148us	4	5	80.00
		kmac_test_vectors_kmac_xof	4.440s	99.697us	4	5	80.00
V2	sideload	kmac_sideload	9.758m	27.399ms	50	50	100.00
V2	app	kmac_app	6.751m	89.840ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.617m	176.879ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.353m	62.985ms	50	50	100.00
V2	error	kmac_error	7.721m	58.809ms	50	50	100.00
V2	key_error	kmac_key_error	19.710s	7.104ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	10.620s	1.674ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	43.730s	1.344ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	39.200s	14.482ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.014m	45.735ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	31.900s	1.797ms	50	50	100.00
V2	stress_all	kmac_stress_all	45.708m	436.266ms	48	50	96.00
V2	intr_test	kmac_intr_test	2.340s	28.656us	50	50	100.00
V2	alert_test	kmac_alert_test	2.370s	22.749us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	5.440s	758.796us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	5.440s	758.796us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.610s	201.998us	5	5	100.00
		kmac_csr_rw	2.740s	31.309us	20	20	100.00
		kmac_csr_aliasing	10.620s	1.920ms	5	5	100.00
		kmac_same_csr_outstanding	4.270s	186.932us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.610s	201.998us	5	5	100.00
		kmac_csr_rw	2.740s	31.309us	20	20	100.00
		kmac_csr_aliasing	10.620s	1.920ms	5	5	100.00
		kmac_same_csr_outstanding	4.270s	186.932us	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.800s	68.954us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.800s	68.954us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.800s	68.954us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.800s	68.954us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	6.000s	198.946us	15	20	75.00
V2S	tl_intg_err	kmac_sec_cm	2.115m	8.070ms	5	5	100.00
		kmac_tl_intg_err	5.750s	781.030us	12	20	60.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.750s	781.030us	12	20	60.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	31.900s	1.797ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.471m	5.009ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.758m	27.399ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.800s	68.954us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	2.115m	8.070ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	2.115m	8.070ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	2.115m	8.070ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.471m	5.009ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	31.900s	1.797ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	2.115m	8.070ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.335m	5.017ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.471m	5.009ms	50	50	100.00
V2S		TOTAL			62	75	82.67
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.941m	20.387ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			919	940	97.77

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.04	99.14	94.47	99.89	77.46	97.09	99.38	97.86

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 12 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 4 failures.

0.kmac_shadow_reg_errors_with_csr_rw.3974915421923431970877244961676430462462321685896181729521194847743823792042
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[44] & 'hffffffff)))'
  UVM_ERROR @  34109705 ps: (kmac_csr_assert_fpv.sv:530) [ASSERT FAILED] prefix_5_rd_A
  UVM_INFO @  34109705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.kmac_shadow_reg_errors_with_csr_rw.646621861078241858618791274469178195036655931358846800045873091492886485461
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[45] & 'hffffffff)))'
  UVM_ERROR @   7272549 ps: (kmac_csr_assert_fpv.sv:536) [ASSERT FAILED] prefix_6_rd_A
  UVM_INFO @   7272549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test kmac_tl_intg_err has 8 failures.

1.kmac_tl_intg_err.48644860105019088865413525200965471046218843007125938428381794776595402085791
Line 90, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffff03ff) == (exp_vals[4] & 'hffff03ff)))'
  UVM_ERROR @  77304703 ps: (kmac_csr_assert_fpv.sv:494) [ASSERT FAILED] entropy_period_rd_A
  UVM_INFO @  77304703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.kmac_tl_intg_err.91175032644405062965869953251726991992673117856377976507380748068585294021715
Line 82, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/2.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[43] & 'hffffffff)))'
  UVM_ERROR @  31246370 ps: (kmac_csr_assert_fpv.sv:524) [ASSERT FAILED] prefix_4_rd_A
  UVM_INFO @  31246370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 4 failures:
- Test kmac_stress_all_with_rand_reset has 4 failures.
  - 0.kmac_stress_all_with_rand_reset.108856000997550826636074071948399488859923078979893527144834187341848787906936
    Line 134, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3990480908 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 3990480908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.kmac_stress_all_with_rand_reset.72220408380841219736462560211247436313128435977102491119762868129972445797069
    Line 187, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16926308589 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 16926308589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.

UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 4 failures:

Test kmac_test_vectors_kmac_xof has 1 failures.

1.kmac_test_vectors_kmac_xof.70286259123703021402317821586007718613597833167677471256002115558329498581637
Line 73, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_test_vectors_kmac_xof/latest/run.log

  UVM_ERROR @  40032704 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  40032704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_kmac has 1 failures.

4.kmac_test_vectors_kmac.86124581593457876144385978911504587069984065626090086261311469002264424521830
Line 73, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/4.kmac_test_vectors_kmac/latest/run.log

  UVM_ERROR @  63428739 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  63428739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 2 failures.

17.kmac_stress_all.57408252797532642407697940082090303444447008839949889350503252506896026132248
Line 189, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/17.kmac_stress_all/latest/run.log

  UVM_ERROR @ 21033160018 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 21033160018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

47.kmac_stress_all.1343252277804670273140735623216868550458539590141226909618627701128465689377
Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/47.kmac_stress_all/latest/run.log

  UVM_ERROR @  48971838 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  48971838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 7.kmac_shadow_reg_errors_with_csr_rw.99693003821591733011235890482320210891724915112479357168122861217497153273639
    Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  58000801 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (457332305 [0x1b425651] vs 569064317 [0x21eb3b7d]) Regname: kmac_reg_block.prefix_9 reset value: 0x0
  UVM_INFO @  58000801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```