KMAC/UNMASKED Simulation Results

Sunday June 08 2025 00:08:59 UTC

GitHub Revision: `2995ba4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.184m	8.246ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.390s	36.153us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.720s	32.547us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.100s	18.031ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.460s	139.785us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.760s	177.158us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.720s	32.547us	20	20	100.00
		kmac_csr_aliasing	7.460s	139.785us	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.540s	19.007us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	3.080s	105.205us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	46.211m	505.510ms	50	50	100.00
V2	burst_write	kmac_burst_write	15.342m	115.257ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	31.197m	351.878ms	5	5	100.00
		kmac_test_vectors_sha3_256	28.700m	90.460ms	5	5	100.00
		kmac_test_vectors_sha3_384	20.482m	67.839ms	5	5	100.00
		kmac_test_vectors_sha3_512	18.771m	180.225ms	5	5	100.00
		kmac_test_vectors_shake_128	35.923m	760.054ms	5	5	100.00
		kmac_test_vectors_shake_256	32.147m	345.801ms	5	5	100.00
		kmac_test_vectors_kmac	3.990s	172.233us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.190s	335.731us	5	5	100.00
V2	sideload	kmac_sideload	6.063m	84.805ms	50	50	100.00
V2	app	kmac_app	6.062m	148.318ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.609m	13.695ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.324m	58.705ms	50	50	100.00
V2	error	kmac_error	6.640m	31.757ms	50	50	100.00
V2	key_error	kmac_key_error	17.830s	7.941ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.705m	10.081ms	35	50	70.00
V2	edn_timeout_error	kmac_edn_timeout_error	43.090s	4.194ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	41.050s	14.016ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.173m	24.180ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	23.130s	3.346ms	50	50	100.00
V2	stress_all	kmac_stress_all	40.872m	184.209ms	50	50	100.00
V2	intr_test	kmac_intr_test	2.470s	24.352us	50	50	100.00
V2	alert_test	kmac_alert_test	2.430s	58.255us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.920s	710.978us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.920s	710.978us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.390s	36.153us	5	5	100.00
		kmac_csr_rw	2.720s	32.547us	20	20	100.00
		kmac_csr_aliasing	7.460s	139.785us	5	5	100.00
		kmac_same_csr_outstanding	3.960s	98.458us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.390s	36.153us	5	5	100.00
		kmac_csr_rw	2.720s	32.547us	20	20	100.00
		kmac_csr_aliasing	7.460s	139.785us	5	5	100.00
		kmac_same_csr_outstanding	3.960s	98.458us	20	20	100.00
V2		TOTAL			725	740	97.97
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.170s	274.114us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.170s	274.114us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.170s	274.114us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.170s	274.114us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	6.340s	378.131us	16	20	80.00
V2S	tl_intg_err	kmac_sec_cm	1.043m	25.365ms	5	5	100.00
		kmac_tl_intg_err	5.010s	301.640us	16	20	80.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.010s	301.640us	16	20	80.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	23.130s	3.346ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.184m	8.246ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.063m	84.805ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.170s	274.114us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.043m	25.365ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.043m	25.365ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.043m	25.365ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.184m	8.246ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	23.130s	3.346ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.043m	25.365ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.833m	28.455ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.184m	8.246ms	50	50	100.00
V2S		TOTAL			67	75	89.33
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.455m	13.413ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			912	940	97.02

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.81	97.23	94.42	100.00	73.55	95.98	99.35	96.13

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 8 failures:

Test kmac_tl_intg_err has 4 failures.

3.kmac_tl_intg_err.40204035732041986464015449463170370869304165437458429162712790101226672995575
Line 82, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/3.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffff03ff) == (exp_vals[4] & 'hffff03ff)))'
  UVM_ERROR @   8747303 ps: (kmac_csr_assert_fpv.sv:494) [ASSERT FAILED] entropy_period_rd_A
  UVM_INFO @   8747303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.kmac_tl_intg_err.6784264039288078168542029933429101438634930212352958323650414056032404830752
Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/10.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[40] & 'hffffffff)))'
  UVM_ERROR @  65144879 ps: (kmac_csr_assert_fpv.sv:506) [ASSERT FAILED] prefix_1_rd_A
  UVM_INFO @  65144879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test kmac_shadow_reg_errors_with_csr_rw has 4 failures.

8.kmac_shadow_reg_errors_with_csr_rw.92490886247608465180801400678559398154434945012668675530994396640597675159462
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[46] & 'hffffffff)))'
  UVM_ERROR @   9603609 ps: (kmac_csr_assert_fpv.sv:542) [ASSERT FAILED] prefix_7_rd_A
  UVM_INFO @   9603609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.kmac_shadow_reg_errors_with_csr_rw.36055286543307761056774812236646341025302708619877126990456661686886470622627
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/12.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[45] & 'hffffffff)))'
  UVM_ERROR @  65390305 ps: (kmac_csr_assert_fpv.sv:536) [ASSERT FAILED] prefix_6_rd_A
  UVM_INFO @  65390305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 0.kmac_stress_all_with_rand_reset.66290290515956716432819052145981549198093688434512891061223300838228542666468
    Line 80, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  11443943 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
  UVM_INFO @  11443943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.kmac_stress_all_with_rand_reset.23742318570487935939904764486214266310395407124587805345962588834309506780442
    Line 187, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3251483843 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 3251483843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 5 failures:
- Test kmac_sideload_invalid has 5 failures.
  - 2.kmac_sideload_invalid.7738354025241552331700284978298090795246996074913231866838271320950349195647
    Line 73, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/2.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10101966103 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x4f033000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
  UVM_INFO @ 10101966103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.kmac_sideload_invalid.18293445359578323776042682089558055949177824429766325979329946512717596046934
    Line 73, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/9.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10008681346 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x789e0000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
  UVM_INFO @ 10008681346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 5.kmac_sideload_invalid.34447072737146660259091942088433153977004965383488416300454075946514393919960
    Line 81, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/5.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10217480214 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x1e852000, Comparison=CompareOpEq, exp_data=0x1, call_count=9)
  UVM_INFO @ 10217480214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 14.kmac_sideload_invalid.18067959528848852722848979522772897782301339555893811842029847166075401168104
    Line 91, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/14.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10121860521 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x28878000, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
  UVM_INFO @ 10121860521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=26) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 16.kmac_sideload_invalid.109064434804218064081886063314740827909296447853851021031006063534610123044496
    Line 98, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/16.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10242059130 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb468f000, Comparison=CompareOpEq, exp_data=0x1, call_count=26)
  UVM_INFO @ 10242059130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 19.kmac_sideload_invalid.38705578903057763084929203406766131483581675239429288279407766383638476616089
    Line 80, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/19.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10176693953 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x270c6000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
  UVM_INFO @ 10176693953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 26.kmac_sideload_invalid.74423675975553849839460016188408554840835618161758525765670487513122029237716
    Line 88, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/26.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10285331581 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x1016e000, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
  UVM_INFO @ 10285331581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 28.kmac_sideload_invalid.105011973057591066068767114833485681396170966776008530318793866357964148146108
    Line 84, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/28.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10372643505 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x78e15000, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
  UVM_INFO @ 10372643505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 32.kmac_sideload_invalid.51692326567358763802482313375258150160438926272005828832379768244144454021545
    Line 85, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/32.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10089909347 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xa7c1000, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
  UVM_INFO @ 10089909347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 34.kmac_sideload_invalid.24794144292007679230605203249603174785795812344287135389695151879465494423884
    Line 77, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/34.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10064392806 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x33f7a000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
  UVM_INFO @ 10064392806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 37.kmac_sideload_invalid.46333610827613756206906634744233032811393161378919550058707775505299186389709
    Line 87, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/37.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10175979214 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x3c26000, Comparison=CompareOpEq, exp_data=0x1, call_count=13)
  UVM_INFO @ 10175979214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 41.kmac_sideload_invalid.69741392786433152008230356200202289397783788917860787183684373178160699656690
    Line 91, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/41.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10081300870 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x3db77000, Comparison=CompareOpEq, exp_data=0x1, call_count=18)
  UVM_INFO @ 10081300870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```