OTBN Simulation Results

Sunday June 08 2025 00:08:59 UTC

GitHub Revision: 2995ba4

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	51.000s	114.576us	1	1	100.00
V1	single_binary	otbn_single	48.000s	16.998us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	13.000s	45.986us	5	5	100.00
V1	csr_rw	otbn_csr_rw	8.000s	14.911us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	10.000s	77.151us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	7.000s	19.483us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	12.000s	38.434us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	8.000s	14.911us	20	20	100.00
		otbn_csr_aliasing	7.000s	19.483us	5	5	100.00
V1	mem_walk	otbn_mem_walk	37.000s	1.822ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	24.000s	1.705ms	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	46.000s	137.524us	10	10	100.00
V2	multi_error	otbn_multi_err	58.000s	587.540us	1	1	100.00
V2	back_to_back	otbn_multi	3.750m	713.606us	10	10	100.00
V2	stress_all	otbn_stress_all	1.633m	422.953us	10	10	100.00
V2	lc_escalation	otbn_escalate	26.000s	315.363us	60	60	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	14.000s	48.510us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	21.000s	76.547us	10	10	100.00
V2	alert_test	otbn_alert_test	11.000s	22.283us	50	50	100.00
V2	intr_test	otbn_intr_test	9.000s	25.317us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	10.000s	40.649us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	10.000s	40.649us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	13.000s	45.986us	5	5	100.00
		otbn_csr_rw	8.000s	14.911us	20	20	100.00
		otbn_csr_aliasing	7.000s	19.483us	5	5	100.00
		otbn_same_csr_outstanding	9.000s	347.129us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	13.000s	45.986us	5	5	100.00
		otbn_csr_rw	8.000s	14.911us	20	20	100.00
		otbn_csr_aliasing	7.000s	19.483us	5	5	100.00
		otbn_same_csr_outstanding	9.000s	347.129us	20	20	100.00
V2		TOTAL			246	246	100.00
V2S	mem_integrity	otbn_imem_err	33.000s	159.654us	10	10	100.00
		otbn_dmem_err	16.000s	50.040us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	15.000s	61.158us	5	5	100.00
		otbn_controller_ispr_rdata_err	13.000s	284.012us	5	5	100.00
		otbn_mac_bignum_acc_err	31.000s	133.299us	5	5	100.00
		otbn_urnd_err	10.000s	24.594us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	11.000s	23.235us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	13.000s	22.123us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	12.000s	59.791us	10	10	100.00
V2S	tl_intg_err	otbn_sec_cm	7.750m	2.187ms	3	5	60.00
		otbn_tl_intg_err	1.033m	279.600us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	44.000s	213.351us	17	20	85.00
V2S	prim_fsm_check	otbn_sec_cm	7.750m	2.187ms	3	5	60.00
V2S	prim_count_check	otbn_sec_cm	7.750m	2.187ms	3	5	60.00
V2S	sec_cm_mem_scramble	otbn_smoke	51.000s	114.576us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	16.000s	50.040us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	33.000s	159.654us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	1.033m	279.600us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	26.000s	315.363us	60	60	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	33.000s	159.654us	10	10	100.00
		otbn_dmem_err	16.000s	50.040us	15	15	100.00
		otbn_zero_state_err_urnd	14.000s	48.510us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	23.235us	5	5	100.00
		otbn_sec_cm	7.750m	2.187ms	3	5	60.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	7.750m	2.187ms	3	5	60.00
V2S	sec_cm_scramble_key_sideload	otbn_single	48.000s	16.998us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	33.000s	159.654us	10	10	100.00
		otbn_dmem_err	16.000s	50.040us	15	15	100.00
		otbn_zero_state_err_urnd	14.000s	48.510us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	23.235us	5	5	100.00
		otbn_sec_cm	7.750m	2.187ms	3	5	60.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	7.750m	2.187ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	26.000s	315.363us	60	60	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	33.000s	159.654us	10	10	100.00
		otbn_dmem_err	16.000s	50.040us	15	15	100.00
		otbn_zero_state_err_urnd	14.000s	48.510us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	23.235us	5	5	100.00
		otbn_sec_cm	7.750m	2.187ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	7.750m	2.187ms	3	5	60.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	48.000s	16.998us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	13.000s	30.842us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	11.000s	27.536us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.817m	287.157us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.817m	287.157us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	15.000s	41.931us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	7.750m	2.187ms	3	5	60.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	7.750m	2.187ms	3	5	60.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	15.000s	114.781us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	7.750m	2.187ms	3	5	60.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	7.750m	2.187ms	3	5	60.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	16.000s	23.759us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	16.000s	23.759us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	15.000s	40.129us	6	7	85.71
V2S	sec_cm_data_mem_sec_wipe	otbn_single	48.000s	16.998us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	48.000s	16.998us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	48.000s	16.998us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	3.750m	713.606us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	48.000s	16.998us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	48.000s	16.998us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	11.000s	19.348us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	48.000s	16.998us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	7.750m	2.187ms	3	5	60.00
V2S		TOTAL			157	163	96.32
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	7.700m	6.128ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			573	585	97.95

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
99.10	99.64	95.95	99.73	93.32	93.43	100.00	97.85	99.57

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:929) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:

  • Test otbn_stress_all_with_rand_reset has 5 failures.

    • 0.otbn_stress_all_with_rand_reset.68663096147668576644520593305657283174236866149411656665935605840828089671635
      Line 633, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6127978481 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 6127978481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 4.otbn_stress_all_with_rand_reset.54343573834503395479291640928179573286013212769081761348316688159791407928172
      Line 335, in log /nightly/runs/scratch/master/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2581858370 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2581858370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.

• UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 2 failures:

  • Test otbn_passthru_mem_tl_intg_err has 2 failures.

    • 0.otbn_passthru_mem_tl_intg_err.111240044133961967952565273042482734991215794859365857675770132283797037115242
      Line 82, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_passthru_mem_tl_intg_err/latest/run.log

        UVM_FATAL @   2563224 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
        UVM_INFO @   2563224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 14.otbn_passthru_mem_tl_intg_err.103390636222709906865918003330661316250832408385899220583520654258758283176123
      Line 87, in log /nightly/runs/scratch/master/otbn-sim-xcelium/14.otbn_passthru_mem_tl_intg_err/latest/run.log

        UVM_FATAL @  17285083 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
        UVM_INFO @  17285083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 2 failures:

  • Test otbn_sec_cm has 2 failures.

    • 1.otbn_sec_cm.42633353441336185637193548809420083331387616434947029016210579329851084404438
      Line 112, in log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 93256075 PS) Assertion tb.dut.ErrBitsKnown_A has failed
        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 93256075 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
        UVM_ERROR @  93256075 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
        UVM_INFO @  93256075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 4.otbn_sec_cm.67310497278360284994916378073269171323523149156916317057311179305130120530577
      Line 84, in log /nightly/runs/scratch/master/otbn-sim-xcelium/4.otbn_sec_cm/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 4599973 PS) Assertion tb.dut.ErrBitsKnown_A has failed
        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 4599973 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
        UVM_ERROR @   4599973 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
        UVM_INFO @   4599973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:

  • Test otbn_sec_wipe_err has 1 failures.

    • 6.otbn_sec_wipe_err.101013387419357267137374804657841103674776195454094613682413771696285197905855
      Line 111, in log /nightly/runs/scratch/master/otbn-sim-xcelium/6.otbn_sec_wipe_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 61221136 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
        UVM_ERROR @  61221136 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @  61221136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:

  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 9.otbn_stress_all_with_rand_reset.45306047910975220663972088867566340242244073547672930475100826505457480496532
      Line 142, in log /nightly/runs/scratch/master/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @   8996331 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
        UVM_INFO @   8996331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:

  • Test otbn_passthru_mem_tl_intg_err has 1 failures.

    • 11.otbn_passthru_mem_tl_intg_err.88639622580749495648864846613041473778051120226271766895055221867258091525249
      Line 87, in log /nightly/runs/scratch/master/otbn-sim-xcelium/11.otbn_passthru_mem_tl_intg_err/latest/run.log

        UVM_FATAL @  40410179 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
        UVM_INFO @  40410179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---