2995ba4| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 7.000s | 143.930us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 4.000s | 14.874us | 5 | 5 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 4.000s | 44.646us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 6.000s | 65.830us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 5.000s | 60.855us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 5.000s | 95.169us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 4.000s | 44.646us | 20 | 20 | 100.00 |
| pattgen_csr_aliasing | 5.000s | 60.855us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | perf | pattgen_perf | 54.667m | 600.000ms | 27 | 50 | 54.00 |
| V2 | cnt_rollover | cnt_rollover | 1.333m | 2.687ms | 50 | 50 | 100.00 |
| V2 | error | pattgen_error | 5.000s | 57.561us | 50 | 50 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 2.892h | 1.401s | 22 | 50 | 44.00 |
| V2 | alert_test | pattgen_alert_test | 5.000s | 12.956us | 50 | 50 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 5.000s | 43.267us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 6.000s | 100.062us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 6.000s | 100.062us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 4.000s | 14.874us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 4.000s | 44.646us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 5.000s | 60.855us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 5.000s | 106.558us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 4.000s | 14.874us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 4.000s | 44.646us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 5.000s | 60.855us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 5.000s | 106.558us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 289 | 340 | 85.00 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 6.000s | 382.656us | 20 | 20 | 100.00 |
| pattgen_sec_cm | 5.000s | 260.693us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 6.000s | 382.656us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 2.333m | 11.385ms | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| Unmapped tests | pattgen_inactive_level | 4.417m | 10.019ms | 35 | 50 | 70.00 | |
| TOTAL | 454 | 570 | 79.65 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.80 | 100.00 | 100.00 | 100.00 | 98.50 | 96.61 | -- | 100.00 | 89.42 |
UVM_ERROR (cip_base_vseq.sv:929) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 50 failures:
0.pattgen_stress_all_with_rand_reset.20998815698813452775076595762124884370532410175279822849853600620555711235996
Line 115, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 908296442 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 908300294 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 908300294 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 908320294 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
1.pattgen_stress_all_with_rand_reset.44960117023473745785800901673790236379360960302811946113769236561131161765522
Line 110, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 114878592 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 114888517 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 114888517 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 114909351 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
... and 48 more failures.
Job timed out after * minutes has 26 failures:
0.pattgen_perf.110036849950862360721591427658303903647722183538127165252114151230409415440457
Log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log
Job timed out after 60 minutes
4.pattgen_perf.97093124567716593055581643114653804429818713171105317810329232808190859857288
Log /nightly/runs/scratch/master/pattgen-sim-xcelium/4.pattgen_perf/latest/run.log
Job timed out after 60 minutes
... and 11 more failures.
7.pattgen_stress_all.52742432801456037821134630579390343565382147532695224003203170835571686566690
Log /nightly/runs/scratch/master/pattgen-sim-xcelium/7.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
12.pattgen_stress_all.95886718308399432636109887629342120121833505687723799887032676017764134821213
Log /nightly/runs/scratch/master/pattgen-sim-xcelium/12.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
... and 11 more failures.
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 15 failures:
1.pattgen_stress_all.107256415055007843047915994286875464315558299009216653027381714875380001219592
Line 144, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all/latest/run.log
UVM_ERROR @ 130654379 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10430
3.pattgen_stress_all.7999014683621955279128172506520477794105363113757279652784861621297160489329
Line 140, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/3.pattgen_stress_all/latest/run.log
UVM_ERROR @ 96042035549 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10299
... and 13 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 10 failures:
1.pattgen_perf.4624801756505198419209253461143919417606573438436942776292100224924599537591
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/1.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.pattgen_perf.85452290138076157819280490166726041569570713947173673054576547955147130550879
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/5.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 3 failures:
23.pattgen_inactive_level.71366195618726143833190542769615672317806386192143400426545602321709929242909
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/23.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10002234870 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xe3417750, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
UVM_INFO @ 10002234870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
40.pattgen_inactive_level.26953616178589876399362134377629346265218796531466488679781917563513784276741
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/40.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10004189685 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xfb05a490, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
UVM_INFO @ 10004189685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 2 failures:
0.pattgen_inactive_level.11302440470253607945992082006028566306031136079760532398507303259186786108291
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10082014102 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x3fe9e250, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
UVM_INFO @ 10082014102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.pattgen_inactive_level.47740046209309351730545391321718235764338191483042319486407627245460560805505
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/13.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10147356132 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xe2718710, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
UVM_INFO @ 10147356132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 2 failures:
20.pattgen_inactive_level.102644448036062752700887150526279787979760683370440761398313025604667998980419
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/20.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10021275789 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x58f2fc10, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10021275789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.pattgen_inactive_level.4197504399966429281960095585219423855362320321359311472704143446730586298984
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/38.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10107343990 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x43865410, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10107343990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=20) has 1 failures:
5.pattgen_inactive_level.61302832268757536015091739288325249192775267981731132391973660154158924934521
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/5.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10018596203 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xaf228b50, Comparison=CompareOpEq, exp_data=0x0, call_count=20)
UVM_INFO @ 10018596203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 1 failures:
10.pattgen_inactive_level.85562284489676544438879671208501425183268212831046212287825442226715171572091
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/10.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10002566470 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xa8851510, Comparison=CompareOpEq, exp_data=0x0, call_count=6)
UVM_INFO @ 10002566470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=24) has 1 failures:
12.pattgen_inactive_level.50120391972447148225228894352584546760423979394812010402110199473621753614775
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/12.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10130641082 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xf2846850, Comparison=CompareOpEq, exp_data=0x0, call_count=24)
UVM_INFO @ 10130641082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=27) has 1 failures:
15.pattgen_inactive_level.12673964328085625104337840294040196920819249172248646658523425467950508796255
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/15.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10250589727 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x4d8d7250, Comparison=CompareOpEq, exp_data=0x0, call_count=27)
UVM_INFO @ 10250589727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
25.pattgen_inactive_level.34602322708966449233373481628855215071833852513420299602213866117194840060954
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/25.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10007355926 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x40d665d0, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
UVM_INFO @ 10007355926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:
36.pattgen_inactive_level.97237762610215181981123429765143492270172562137848407059385447203931039073427
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/36.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10006060581 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x8aeda790, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
UVM_INFO @ 10006060581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
39.pattgen_inactive_level.95776737694696271213898588534889605121600028042152129768667008487900986522951
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/39.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10065612958 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x5ae6fd90, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
UVM_INFO @ 10065612958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23) has 1 failures:
44.pattgen_inactive_level.106323040758588610594694705431477618712970939757754609955772568312018514394469
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/44.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10044118448 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x4de5d9d0, Comparison=CompareOpEq, exp_data=0x0, call_count=23)
UVM_INFO @ 10044118448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---