ROM_CTRL/32KB Simulation Results

Sunday June 08 2025 00:08:59 UTC

GitHub Revision: 2995ba4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	6.230s	577.089us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	8.040s	293.360us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	6.870s	299.579us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	6.680s	484.788us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	7.730s	170.556us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	7.780s	548.491us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	6.870s	299.579us	20	20	100.00
		rom_ctrl_csr_aliasing	7.730s	170.556us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	7.060s	132.859us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	7.730s	186.256us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	5.900s	136.269us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	24.260s	637.551us	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	8.840s	547.465us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	7.410s	168.527us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	10.670s	173.443us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	10.670s	173.443us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	8.040s	293.360us	5	5	100.00
		rom_ctrl_csr_rw	6.870s	299.579us	20	20	100.00
		rom_ctrl_csr_aliasing	7.730s	170.556us	5	5	100.00
		rom_ctrl_same_csr_outstanding	8.970s	319.370us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	8.040s	293.360us	5	5	100.00
		rom_ctrl_csr_rw	6.870s	299.579us	20	20	100.00
		rom_ctrl_csr_aliasing	7.730s	170.556us	5	5	100.00
		rom_ctrl_same_csr_outstanding	8.970s	319.370us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	2.222m	38.265ms	15	20	75.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	36.830s	3.174ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.518m	936.163us	5	5	100.00
		rom_ctrl_tl_intg_err	1.030m	424.529us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.518m	936.163us	5	5	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	3.518m	936.163us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.222m	38.265ms	15	20	75.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.222m	38.265ms	15	20	75.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.222m	38.265ms	15	20	75.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.222m	38.265ms	15	20	75.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.222m	38.265ms	15	20	75.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.518m	936.163us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.518m	936.163us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	6.230s	577.089us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	6.230s	577.089us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	6.230s	577.089us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.030m	424.529us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.222m	38.265ms	15	20	75.00
		rom_ctrl_kmac_err_chk	8.840s	547.465us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	2.222m	38.265ms	15	20	75.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.222m	38.265ms	15	20	75.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	2.222m	38.265ms	15	20	75.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	36.830s	3.174ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.518m	936.163us	5	5	100.00
V2S		TOTAL			60	65	92.31
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	6.113m	6.577ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			261	266	98.12

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.73	99.41	100.00	100.00	100.00	98.98	99.28

Failure Buckets

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 5 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 5 failures.

    • 2.rom_ctrl_corrupt_sig_fatal_chk.45194884060482896075886579501319082712613203707287215448871152395268535430264
      Line 99, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 5480838889 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 5480838889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 7.rom_ctrl_corrupt_sig_fatal_chk.66109383469363665636327280707382911499196886099737274560589856340968303316126
      Line 90, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 709248411 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 709248411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.