RV_TIMER Simulation Results

Sunday June 08 2025 00:08:59 UTC

GitHub Revision: 2995ba4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	2.130s	26.318us	20	20	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	2.030s	11.770us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	2.210s	58.274us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.910s	90.836us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	2.210s	56.425us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	2.760s	143.919us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	2.210s	58.274us	20	20	100.00
		rv_timer_csr_aliasing	2.210s	56.425us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	random_reset	rv_timer_random_reset	19.220s	39.309ms	20	20	100.00
V2	disabled	rv_timer_disabled	6.540s	2.422ms	20	20	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	12.489m	473.319ms	10	10	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	12.489m	473.319ms	10	10	100.00
V2	stress	rv_timer_stress_all	9.210s	3.708ms	20	20	100.00
V2	alert_test	rv_timer_alert_test	2.130s	24.398us	50	50	100.00
V2	intr_test	rv_timer_intr_test	2.180s	15.986us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.900s	50.163us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.900s	50.163us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	2.030s	11.770us	5	5	100.00
		rv_timer_csr_rw	2.210s	58.274us	20	20	100.00
		rv_timer_csr_aliasing	2.210s	56.425us	5	5	100.00
		rv_timer_same_csr_outstanding	2.390s	42.923us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	2.030s	11.770us	5	5	100.00
		rv_timer_csr_rw	2.210s	58.274us	20	20	100.00
		rv_timer_csr_aliasing	2.210s	56.425us	5	5	100.00
		rv_timer_same_csr_outstanding	2.390s	42.923us	20	20	100.00
V2		TOTAL			210	210	100.00
V2S	tl_intg_err	rv_timer_sec_cm	2.640s	404.740us	5	5	100.00
		rv_timer_tl_intg_err	2.830s	525.278us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.830s	525.278us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	56.290s	24.837ms	20	20	100.00
V3		TOTAL			20	20	100.00
	Unmapped tests	rv_timer_min	2.150s	26.054us	10	10	100.00
		rv_timer_max	2.080s	12.827us	10	10	100.00
		TOTAL			350	350	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.44	100.00	100.00	78.66	--	100.00	100.00	100.00