SPI_DEVICE/1R1W Simulation Results

Sunday June 08 2025 00:08:59 UTC

GitHub Revision: `2995ba4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	6.863m	55.550ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.700s	68.597us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	4.090s	92.685us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	30.220s	7.541ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	21.610s	322.284us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.120s	58.223us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	4.090s	92.685us	20	20	100.00
		spi_device_csr_aliasing	21.610s	322.284us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	2.110s	38.884us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.810s	29.484us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	2.390s	17.449us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	2.270s	1.714us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	1.960s	3.501us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	11.170s	551.072us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	11.170s	551.072us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	32.610s	8.679ms	50	50	100.00
		spi_device_tpm_sts_read	2.530s	58.270us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.075m	182.770ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	36.160s	13.233ms	50	50	100.00
		spi_device_flash_all	5.135m	230.176ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	38.620s	28.300ms	50	50	100.00
		spi_device_flash_all	5.135m	230.176ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	38.620s	28.300ms	50	50	100.00
		spi_device_flash_all	5.135m	230.176ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	5.135m	230.176ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	22.800s	2.196ms	50	50	100.00
		spi_device_flash_all	5.135m	230.176ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	22.800s	2.196ms	50	50	100.00
		spi_device_flash_all	5.135m	230.176ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	22.800s	2.196ms	50	50	100.00
		spi_device_flash_all	5.135m	230.176ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	22.800s	2.196ms	50	50	100.00
		spi_device_flash_all	5.135m	230.176ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	22.800s	2.196ms	50	50	100.00
		spi_device_flash_all	5.135m	230.176ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	38.320s	10.721ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.722m	86.237ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.722m	86.237ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.722m	86.237ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	47.010s	40.588ms	50	50	100.00
		spi_device_read_buffer_direct	22.720s	5.729ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.722m	86.237ms	50	50	100.00
		spi_device_flash_all	5.135m	230.176ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	5.135m	230.176ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	5.135m	230.176ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	33.650s	14.721ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	33.650s	14.721ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	6.863m	55.550ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.112m	172.879ms	50	50	100.00
V2	stress_all	spi_device_stress_all	18.648m	145.456ms	50	50	100.00
V2	alert_test	spi_device_alert_test	2.310s	14.246us	50	50	100.00
V2	intr_test	spi_device_intr_test	2.360s	11.917us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.010s	189.648us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.010s	189.648us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.700s	68.597us	5	5	100.00
		spi_device_csr_rw	4.090s	92.685us	20	20	100.00
		spi_device_csr_aliasing	21.610s	322.284us	5	5	100.00
		spi_device_same_csr_outstanding	5.590s	1.015ms	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.700s	68.597us	5	5	100.00
		spi_device_csr_rw	4.090s	92.685us	20	20	100.00
		spi_device_csr_aliasing	21.610s	322.284us	5	5	100.00
		spi_device_same_csr_outstanding	5.590s	1.015ms	20	20	100.00
V2		TOTAL			940	961	97.81
V2S	tl_intg_err	spi_device_sec_cm	2.870s	318.395us	5	5	100.00
		spi_device_tl_intg_err	23.480s	1.104ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.480s	1.104ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.393m	227.171ms	49	50	98.00
		TOTAL			1129	1151	98.09

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.80	99.11	96.52	71.19	89.36	98.39	95.76	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.2213554113418322865860055659581316303726556469325007300981403607475860829707
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @  21228832 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[84])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @  21228832 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @  21228832 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[980])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.35009160116083694167125551792254382045741798911260387301087164069802200712582
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   2032349 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[3])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   2032349 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   2032349 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[899])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

Test spi_device_ram_cfg has 1 failures.

0.spi_device_ram_cfg.110741387694081131947163061894575506462624263189146189656542866354021364946596
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

  UVM_ERROR @   1079133 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x281c63 [1010000001110001100011] vs 0x0 [0])
  UVM_ERROR @   1120133 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd3d8b0 [110100111101100010110000] vs 0x0 [0])
  UVM_ERROR @   1139133 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd3e4b2 [110100111110010010110010] vs 0x0 [0])
  UVM_ERROR @   1175133 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1535c0 [101010011010111000000] vs 0x0 [0])
  UVM_ERROR @   1190133 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe043fd [111000000100001111111101] vs 0x0 [0])

Job timed out after * minutes has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 26.spi_device_flash_mode_ignore_cmds.30994784989713209706756036230682628729013937296356002939136831586205087810213
    Log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/26.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  Job timed out after 60 minutes
```